Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion

Publication Information

Title

Japanese:
English:	Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion

Author

Japanese:	Tomoyuki Yoda, 高橋篤司.
English:	Tomoyuki Yoda, Atsushi Takahashi.

Language

English

Journal/Book name

Japanese:
English:	IEICE Trans. Fundamentals

Volume, Number, Page

Vol. E82-A No. 11 pp. 2383-2389

Published date

Nov. 1, 1999

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:

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