準同期式設計による乗算器の作成

Publication Information

Title

Japanese:	準同期式設計による乗算器の作成
English:	A synthesis of multiplier based on semi-synchronous design

Author

Japanese:	内海哲章, 高橋篤司.
English:	Tetsuaki Utsumi, Atsushi Takahashi.

Language

Japanese

Journal/Book name

Japanese:	電子情報通信学会技術研究報告 (VLD2000-2)
English:	IEICE Technical Report (VLD2000-2)

Volume, Number, Page

Vol. 100 No. 35 pp. 9-14

Published date

May 11, 2000

Publisher

Japanese:
English:

Conference name

Japanese:	VLSI設計技術研究会
English:	Technical Committee on VLSI Design Technologies

Conference site

Japanese:
English: