Japanese
Home
Search
Horizontal Search
Publication Search
( Advanced Search )
Patent Search
( Advanced Search )
Research Highlight Search
( Advanced Search )
Researcher Search
Search by Organization
Support
FAQ
T2R2 User Registration
Doctoral thesis registration
Support/Contact
About T2R2
What's T2R2?
Operation Guidance
Leaflets
About file disclosure
Related Links
Tokyo Tech
STAR Search
NII IR Program
Home
>
Help
Publication Information
Title
Japanese:
準同期方式によるLSIのピーク電力の削減
English:
Reduction of peak power in LSI by using semi-synchronous circuit design
Author
Japanese:
森創司,
高橋篤司
.
English:
Soji Mori,
Atsushi Takahashi
.
Language
Japanese
Journal/Book name
Japanese:
電子情報通信学会技術研究報告 (VLD2003-141)
English:
IEICE Technical Report (VLD2003-141)
Volume, Number, Page
Vol. 103 No. 702 pp. 31-36
Published date
Mar. 11, 2004
Publisher
Japanese:
English:
Conference name
Japanese:
VLSI設計技術研究会
English:
Technical Committee on VLSI Design Technologies
Conference site
Japanese:
English:
©2007
Tokyo Institute of Technology All rights reserved.