A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework

Publication Information

Title

Japanese:	一般同期方式におけるレジスタ再配置によるレジスタ削減手法
English:	A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework

Author

Japanese:	小平行秀, 高橋篤司.
English:	Yukihide Kohira, Atsushi Takahashi.

Language

English

Journal/Book name

Japanese:	電子情報通信学会技術研究報告 (VLD2006-70)
English:	IEICE Technical Report (VLD2006-70)

Volume, Number, Page

Vol. 106 No. 388 pp. 33-38

Published date

Nov. 2006

Publisher

Japanese:
English:

Conference name

Japanese:	VLSI設計技術研究会
English:	Technical Committee on VLSI Design Technologies

Conference site

Japanese:
English:

Official URL