【IMPORTANT】T2R2 and STAR Search: Service Discontinuation and Successor Systems Japanese

Home > Help Publication Information Title Japanese: ゲートレベルの遅延挿入による準同期式回路のクロック周期の最小化  English: Clock Period Minimization of Semi-Synchronous Circuits by Gate Level Delay Insertion  Author Japanese: 依田友幸, 高橋篤司, 梶谷洋司.   English: Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani.   Language Japanese  Journal/Book name Japanese: DAシンポジウム'98 論文集, 情報処理学会シンポジウムシリーズ  English: Proc. DA Symposium '98, IPSJ Symposium Series  Volume, Number, Page Vol. 98    No. 9    pp. 233-238 Published date July 18, 1998  Publisher Japanese:   English:   Conference name Japanese:   English:   Conference site Japanese:   English:

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