準同期式回路における遅延最適化によるクロック高速化

Publication Information

Title

Japanese:	準同期式回路における遅延最適化によるクロック高速化
English:	Clock-period minimization by delay optimization on the semi-synchronous circuit

Author

Japanese:	森下和明, 高橋篤司, 梶谷洋司.
English:	Kazuaki Morishita, Atsushi Takahashi, Yoji Kajitani.

Language

Japanese

Journal/Book name

Japanese:	情報処理学会研究報告 (97-DA-83)
English:	IPSJ SIG Technical Reports (97-DA-83)

Volume, Number, Page

Vol. 97 No. 17 pp. 73-80

Published date

Feb. 14, 1997

Publisher

Japanese:
English:

Conference name

Japanese:	設計自動化研究会
English:	Design Automation

Conference site

Japanese:
English: