A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework

Publication Information

Title

Japanese:
English:	A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework

Author

Japanese:	小平行秀, 高橋篤司.
English:	Yukihide Kohira, Atsushi Takahashi.

Language

English

Journal/Book name

Japanese:
English:	IEICE Trans. Fundamentals

Volume, Number, Page

Vol. E91-A No. 10 pp. 3030-3037

Published date

Oct. 1, 2008

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:

File

DOI