クロック周期短縮のための挿入遅延量を抑えた回路への遅延挿入法

Publication Information

Title

Japanese:	クロック周期短縮のための挿入遅延量を抑えた回路への遅延挿入法
English:	A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits

Author

Japanese:	谷修平, 小平行秀, 高橋篤司.
English:	Shuhei Tani, Yukihide Kohira, Atsushi Takahashi.

Language

Japanese

Journal/Book name

Japanese:	電子情報通信学会技術研究報告 (VLD2008-135)
English:	IEICE Technical Report (VLD2008-135)

Volume, Number, Page

Vol. 108 No. 487 pp. 53-58

Published date

Mar. 11, 2009

Publisher

Japanese:
English:

Conference name

Japanese:	VLSI設計技術研究会
English:	Technical Committee on VLSI Design Technologies

Conference site

Japanese:	那覇市（沖縄県）
English: