Static noise margin and power-gating efficiency of a new nonvolatile SRAM cell based on pseudo-spin-transistor architecture

Publication Information

Title

Japanese:
English:	Static noise margin and power-gating efficiency of a new nonvolatile SRAM cell based on pseudo-spin-transistor architecture

Author

Japanese:	周藤悠介, 山本修一郎, 菅原聡.
English:	Y. Shuto, S. Yamamoto, S. Sugahara.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

Published date

May 20, 2012

Publisher

Japanese:
English:

Conference name

Japanese:
English:	4th IEEE Int. Memory Technology Workshop (IMW2012)

Conference site

Japanese:
English:	Milano