強パス遅延テスト可能な論理回路の解析と合成

Publication Information

Title

Japanese:	強パス遅延テスト可能な論理回路の解析と合成
English:	On Synthesis of Robustly Delay-Tetable Combinational Logic Circuits

Author

Japanese:	秋山陽子, 高橋篤司, 梶谷洋司.
English:	Yoko Akiyama, Atsushi Takahashi, Yoji Kajitani.

Language

Japanese

Journal/Book name

Japanese:	電子情報通信学会技術研究報告 (CAS94-124)
English:	IEICE Technical Report (CAS94-124)

Volume, Number, Page

Vol. 94 No. 530 pp. 25-32

Published date

Mar. 1995

Publisher

Japanese:
English:

Conference name

Japanese:	回路とシステム研究会
English:	Technical Committee on Circuits and Systems

Conference site

Japanese:
English: