On-Chip Router Architecture for Detecting Soft Errors | Tokyo Tech Research Repository (T2R2)

Publication Information

Title

Japanese:
English:	On-Chip Router Architecture for Detecting Soft Errors

Author

Japanese:	五十嵐俊哉, 笹河良介, 吉瀬謙二.
English:	Shunya Igarashi, Ryosuke Sasakawa, Kenji Kise.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

Published date

Mar. 8, 2013

Publisher

Japanese:
English:

Conference name

Japanese:	情報処理学会第75回全国大会
English:

Conference site

Japanese:	仙台
English:

©2007 Tokyo Institute of Technology All rights reserved.