Hierarchical BSG floorplan for hierarchical VLSI circuit design

Publication Information

Title

Japanese:
English:	Hierarchical BSG floorplan for hierarchical VLSI circuit design

Author

Japanese:	Zhonglin Wu, Shigetoshi Nakatake, 高橋篤司, 梶谷洋司.
English:	Zhonglin Wu, Shigetoshi Nakatake, Atsushi Takahashi, Yoji Kajitani.

Language

English

Journal/Book name

Japanese:
English:	Electronics and Communications in Japan (Part III: Fundamental Electronic Science)

Volume, Number, Page

Vol. 85 No. 3 pp. 12-21

Published date

Mar. 2002

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:

DOI