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Home > Help Publication Information Title Japanese:   English: Clock period minimization of semi-synchronous circuits by gate-level delay insertion  Author Japanese: Tomoyuki Yoda, 高橋篤司, 梶谷 洋司.   English: Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani.   Language English  Journal/Book name Japanese:   English: Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 1999)  Volume, Number, Page         pp. 125-128 Published date Jan. 1999  Publisher Japanese:   English:   Conference name Japanese:   English:   Conference site Japanese:   English:   DOI https://doi.org/10.1109/ASPDAC.1999.759775

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