Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection

Publication Information

Title

Japanese:
English:	Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection

Author

Japanese:	佐藤真平, 中塚裕志, 高橋篤司.
English:	Shimpei Sato, Hiroshi Nakatsuka, Atsushi Takahashi.

Language

English

Journal/Book name

Japanese:
English:	Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016)

Volume, Number, Page

pp. 60-65

Published date

Oct. 24, 2016

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:	Kyoto

Official URL