Cost-Effective and High-Throughput Merge Network Architecture for the Fastest FPGA Sorting Accelerator

Publication Information

Title

Japanese:
English:	Cost-Effective and High-Throughput Merge Network Architecture for the Fastest FPGA Sorting Accelerator

Author

Japanese:	眞下達, Chu Van Thiem, 吉瀬謙二.
English:	Susumu Mashimo, Thiem Van Chu, Kenji Kise.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

pp. 7-12

Published date

July 26, 2016

Publisher

Japanese:
English:

Conference name

Japanese:
English:	International Symposium on High-Efficient Accelerators ajd Reconfigurable Technologies (Heart 2016)

Conference site

Japanese:
English: