A New Store Energy and Latency Reduction Architecture for Nonvolatile SRAM Using STT-MTJs: Proactive Useless Data Flush Architecture

Publication Information

Title

Japanese:
English:	A New Store Energy and Latency Reduction Architecture for Nonvolatile SRAM Using STT-MTJs: Proactive Useless Data Flush Architecture

Author

Japanese:	北形大樹, 山本修一郎, 菅原聡.
English:	D. Kitagata, S. Yamamoto, S. Sugahara.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

Published date

Dec. 7, 2019

Publisher

Japanese:
English:

Conference name

Japanese:
English:	IEEE International Electron Devices Meeting (IEDM) 2019 MRAM special session

Conference site

Japanese:
English:	San Francisco