STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
Author
Japanese:
Yamamoto K.,
安藤 洸太,
Metrig N.,
Takemoto T.,
Teramoto H.,
Sakai A.,
Takamaeda-Yamazaki S.,
本村 真人.
English:
Yamamoto K.,
Ando K.,
Metrig N.,
Takemoto T.,
Teramoto H.,
Sakai A.,
Takamaeda-Yamazaki S.,
Motomura M..
Language
English
Journal/Book name
Japanese:
English:
Volume, Number, Page
Published date
Feb. 2020
Publisher
Japanese:
English:
Conference name
Japanese:
English:
2020 IEEE International Solid-State Circuits Conference (ISSCC)