Bottleneck Channel Routing to Reduce the Area of Analog VLSI

Publication Information

Title

Japanese:
English:	Bottleneck Channel Routing to Reduce the Area of Analog VLSI

Author

Japanese:	谷口和弥, 田湯智, 高橋篤司, 轟祐吉, 南誠.
English:	Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Yukichi Todoroki, Makoto Minami.

Language

English

Journal/Book name

Japanese:
English:	Proc. the 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2022)

Volume, Number, Page

pp. 26-31

Published date

Oct. 2022

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:

Official URL