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Title
Japanese:FPGAの消費電力を削減するHDLコーディング手法の検討 
English: 
Author
Japanese: 小林諒平, 吉瀬謙二.  
English: Ryohei Kobayashi, Kenji Kise.  
Language Japanese 
Journal/Book name
Japanese:第76回全国大会講演論文集 
English: 
Volume, Number, Page Vol. 2014    No. 1    pp. 25-26
Published date Mar. 2014 
Publisher
Japanese: 
English: 
Conference name
Japanese: 
English: 
Conference site
Japanese: 
English: 
Abstract The advantages of using FPGAs (Field Programmable Gate Arrays) are to change design easily, low respin costs and speeding up development time. However to get these benefits, the FPGA has disadvantages: higher power consumption, larger silicon areas and lower operating speeds compared with the ASIC. In particular, higher power consumption not only requires higher packaging costs, shortens chip life-times, expensive cooling systems, but also decreases system reliability. Therefore, it is truly important to reduce FPGA s power consumption. In this paper, we compare HDL (Hardware Description Language) coding styles, which have already been proposed to reduce power consumption for FPGAs, and seek a more effective way than those.

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