Home >

news Help

Publication Information


Title
Japanese: 
English:Design of Synchronization Mechanism to Conquer the Clock Oscillator Variation for High Performance Stencil Computation Accelerator 
Author
Japanese: 小林 諒平, 高前田(山崎)伸也, 吉瀬 謙二.  
English: Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise.  
Language English 
Journal/Book name
Japanese: 
English:第75回全国大会講演論文集 
Volume, Number, Page Vol. 2013    No. 1    pp. 133-134
Published date Mar. 2013 
Publisher
Japanese: 
English: 
Conference name
Japanese:情報処理学会第75回全国大会 
English: 
Conference site
Japanese:仙台 
English: 
Abstract Stencil computation is one of the typical scientific computing kernels. It is applied diverse areas as Earthquake simulation, seismic imaging for the oil and gas exploration industry. We have proposed the effective stencil computation method and the architecture by employing multiple small FPGAs with 2Dmech topology. However, as we implemented stencil computation accelerator, we realized that the accelerator does not stable operate because clock oscillator variation occurs. This variation occurs because each FPGA node which composes the accelerator has unique clock domain. In this paper, we evaluate clock oscillator variation quantitatively and describe design of synchronization mechanism to conquer the variation to operate the accelerator successfully.

©2007 Institute of Science Tokyo All rights reserved.