Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W

Publication Information

Title

Japanese:
English:	Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W

Author

Japanese:	塩津勇作, 菅原聡.
English:	Yusaku Shiotsu, SATOSHI SUGAHARA.

Language

English

Journal/Book name

Japanese:
English:	IEEE J. Explor. Solid-State Comput. Devices Circuits

Volume, Number, Page

Vol. 11 pp. 25-13

Published date

Mar. 10, 2025

Publisher

Japanese:
English:	IEEE

Conference name

Japanese:
English:

Conference site

Japanese:
English:

DOI