Thin-film transistors (TFTs) made of transparent channel semiconductors such as ZnO are of great technological importance because their insensitivity to visible light makes device structures simple. In fact, there have been several demonstrations of ZnO TFTs achieving reasonably good field effect mobilities of 1-10 cm2/V s, but the overall performance of ZnO TFTs has not been satisfactory, probably due to the presence of dense grain boundaries. We modeled grain boundaries in ZnO TFTs and performed simulation of a ZnO TFT by using a two-dimensional device simulator in order to determine the grain boundary effects on device performance. Polycrystalline ZnO TFT modeling was started by considering a single grain boundary in the middle of the TFT channel, formulated with a Gaussian defect distribution localized in the grain boundary. A double Schottky barrier was formed in the grain boundary, and its barrier height was analyzed as a function of defect density and gate bias. The simulation was extended to TFTs with many grain boundaries to quantitatively analyze the potential profiles that developed along the channel. One of the main differences between a polycrystalline ZnO TFT and a polycrystalline Si TFT is that the much smaller nanoscaled grains in a polycrystalline ZnO TFT induces a strong overlap of the double Schottky barriers with a higher activation energy in the crystallite and a lower barrier potential in the grain boundary at subthreshold or off-state region of its transfer characteristics. Through the simulation, we were able to estimate the density of total trap states localized in the grain boundaries for polycrystalline ZnO TFT by determining the apparent mobility and grain size in the device.
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