Home >

news ヘルプ

論文・著書情報


タイトル
和文: 
英文:Warpage-free Ultra-Thinning ranged from 2 to 5-μm for DRAM Wafers and Evaluation of Devices Characteristics 
著者
和文: YOUNGSUK KIM, S. Kodama, 水島 賢子, 中村 友二, N. Maeda, K. Fujimoto, A. Kawai, 大場 隆之.  
英文: Y. S. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, T. Ohba.  
言語 English 
掲載誌/書名
和文: 
英文:Electronic Components and Technology Conference (ECTC), 2016 IEEE 66th 
巻, 号, ページ         pp. 1471-1476
出版年月 2016年6月 
出版者
和文: 
英文:IEEE 
会議名称
和文: 
英文:2016 IEEE 66th Electronic Components and Technology Conference 
開催地
和文: 
英文:LasVegas 
DOI https://doi.org/10.1109/ECTC.2016.168
アブストラクト An ultra-thinning down to 2.6-μm using 300-mm 2Gb DRAM wafer has been developed. Effects of Si thickness andCu contamination at wafer backside in terms of DRAM yield and retention characteristics are described. Total thickness variation (TTV) after thinning was below 1.9-μm within 300-mm wafer. A degradation of retention characteristics occurred after thinning down to 2.6-μm while no degradationafter thinning down to 5.6-μm for both wafer and package level test were found. In-depth analysis such as stressvariations and distributions, and behavior of Cu diffusion from the back side of ultra-thinned DRAM wafer areevaluated using by TEM, EDX, TOF-SIMS, Positron annihilation spectroscopy (PAS), and μ-Raman spectroscopy.

©2007 Institute of Science Tokyo All rights reserved.