"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","Two-layer Bottleneck Channel Track Assignment for Analog VLSI",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 17",,"pp. 67-76",2024,June
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP",,"Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024)",,,,"pp. 50-55",2024,Mar.
"谷口和弥,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","端子上下配置3層ボトルネック配線に対するトラック割当て法の提案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2023-103)",,"Vol. 123","No. 390","pp. 24-29",2024,Feb.
"谷口和弥,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","整数計画法を用いた3層ボトルネックチャネルトラック割当て法",,"DAシンポジウム2023 論文集",,,,"pp. 199-206",2023,Aug.
"谷口和弥,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","ボトルネック配線における配線可能性向上のための配線交差を考慮したトラック割当て法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-101)",,"Vol. 122","No. 402","pp. 149-154",2023,Mar.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Yukichi Todoroki,Makoto Minami","Bottleneck Channel Routing to Reduce the Area of Analog VLSI",,"Proc. the 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2022)",,,,"pp. 26-31",2022,Oct.
"谷口和弥,田湯智,高橋篤司,轟祐吉,南誠","アナログ集積回路面積削減のためのボトルネックチャネル配線の提案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2021-77)",,"Vol. 121","No. 412","pp. 7-12",2022,Mar.