"Kenichi Okada,Teerachot Siriburanon,Satoshi Kondo,Kento Kimura,Tomohiro Ueno,Satoshi Kawashima,Tohru Kaneko,Wei Deng","A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture",,"IEEE Journal of Solid-State Circuits",,"Vol. 51","No. 6","pp. 1385-1397",2016,June
"Teerachot Siriburanon,近藤 智史,木村 健将,上野 智大,川嶋 理史,金子 徹,Wei Deng,宮原 正也,岡田 健一,松澤 昭","A Digital Sub-sampling ADC-PLL with -112dBc/Hz In-band Phase Noise and 380fsrms Jitter","電子情報通信学会 アナログRF研究会",,,,,,2015,Mar.
"川嶋理史,宮原正也,松澤昭","低電源電圧における電流型DACと抵抗型DACの比較","電子情報通信学会 総合大会",,,,,,2015,Mar.
"菅原 光俊,盛健次,徐 祖楽,川嶋理史,宮原正也,松澤 昭","自動設計に適したレイアウト・ドリブンによるミックストシグナルLSI設計手法のGHz PLL等への適用拡大",,,,"Vol. ECT15","No. 030",,2015,Mar.
"菅原光俊,盛健次,川嶋理史,宮原正也,松澤昭","新規高効率高周波電力出力回路の提案","電子情報通信学会アナログRF研究会",,,,,,2015,Mar.
"Teerachot Siriburanon,Satoshi Kondo,Kento Kimura,Tomohiro Ueno,Satoshi Kawashima,Tohru Kaneko,Wei Deng,Masaya Miyahara,Kenichi Okada,Akira Matsuzawa","A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture","IEEE International Solid-State Circuits Conference (ISSCC),",,,,,,2015,Feb.
"川嶋理史,宮原正也,松澤昭","低雑音ダイナミック比較器の低消費電力化の検討","電子情報通信学会 ソサイエティ大会",,,,,,2013,Sept.