"Zezhong Wang,Masayuki Shimoda,Atsushi Takahashi","BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem",,"Proc. IEEE International Symposium on Circuits and Systems (ISCAS '24)",,,,,2024,May
"Zezhong Wang,Masayuki Shimoda,Atsushi Takahashi","Single Trunk Routing Problem for Generalized Channel","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2023-104)",,"Vol. 123","No. 390","pp. 30-35",2024,Feb.
"佐田 悠生,下田 将之,佐藤 真平,中原 啓貴","畳み込みニューラルネットワークを用いた単眼深度推定のFPGA実装について",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 373","pp. 73-78",2020,Jan.
"倉持 亮佑,佐田 悠生,下田 将之,佐藤 真平,中原 啓貴","アンサンブル学習を用いたスパースCNNのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 373","pp. 67-72",2020,Jan.
"Ryosuke Kuramochi,Masayuki Shimoda,Youki Sada,Shimpei Sato,Hiroki Nakahara","FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System","The 2019 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2019)",,,,,"pp. 1-5",2019,Dec.
"Ryosuke Kuramochi,Youki Sada,Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks","IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '19)",,,,,,2019,Oct.
"Hiroki Nakahara,Youki Sada,Masayuki Shimoda,Kouki Sayama,Akira Jinguji,Shimpei Sato","FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network",,,,,,,2019,Sept.
"倉持亮佑,下田将之,佐田悠生,佐藤真平,中原啓貴","サーマル画像に対する歩行者検出とそのFPGA実装について",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 208","pp. 31-36",2019,Sept.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 5","pp. 1020-1028",2019,May
"佐田悠生,下田将之,佐藤真平,中原啓貴","マルチパス構造を持つ意味的領域分割モデルのFPGA実装",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 457","pp. 49-54",2019,May
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Masayuki Shimoda,Shimpei Sato","GUINNESS: A GUI based Binarized Deep Neural Network Framework for Software Programmers",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 5","pp. 1003-1011",2019,May
"Hiroki Nakahara,Akira Jinguji,Masayuki Shimoda,Shimpei Sato","An FPGA-based Fine Tuning Accelerator for a Sparse CNN","The 27th International Symposium on Field-Programmable Gate Arrays (FPGA '19)",,,,,"pp. 186-186",2019,Feb.
"下田将之,佐藤真平,中原啓貴","ディープニューロ・ファジィによる偽陰性数の削減とその専用回路のFPGA実装の検討","第32回多値論理とその応用研究会",,,,,,2019,Jan.
"佐田悠生,下田将之,佐藤真平,中原啓貴","Intel社OpenCLを用いた3状態CNNの実装に関して","第32回多値論理とその応用研究会",,,,,,2019,Jan.
"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector","The 2018 International Conference on Field-Programmable Technology (FPT '18)",,,,,,2018,Dec.
"佐田悠生,下田将之,佐藤真平,中原啓貴","Intel OpenCLを用いた3状態YOLOv2のFPGA実装について",,"電子情報通信学会技術研究報告",,"vol. 118","no. 340","pp. 7-12",2018,Dec.
"中原啓貴,下田将之,佐藤真平","重み3状態ディープニューラルネットワークを用いた一般物体アルゴリズムYOLOv2のFPGA実装法について","第41回 多値論理フォーラム",,,,,,2018,Sept.
"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2)","The 28th International Conference on Field-programmable Logic and Applications (FPL 2018)",,,,,,2018,Aug.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Demonstration of Object Detection for an event-driven camera","The 28th International Conference on Field-programmable Logic and Applications (FPL 2018)",,,,,,2018,Aug.
"下田将之,佐藤真平,中原啓貴","ディープニューロ・ファジィによる偽陰性数の削減とそのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 165","pp. 211-216",2018,July
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Power Efficient Object Detector with an Event-Driven Camera on an FPGA","The 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2018)",,,,,,2018,June
"中原啓貴,下田将之,佐藤真平","3状態CNNを用いたYOLOv2のFPGA実現に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 63","pp. 87-92",2018,May
"下田将之,佐藤真平,中原啓貴","イベント駆動カメラを用いた物体検出システムのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 63","pp. 81-86",2018,May
"下田将之,佐藤真平,中原啓貴","全2値化畳み込みニューラルネットワークとそのFPGA実装について ? FPT2017デザインコンテスト参加報告 ?",,"電子情報通信学会技術研究報告",,"vol. 117","no. 379","pp. 7-11",2018,Jan.
"下田将之,佐藤真平,中原啓貴","ディープニューロファジィの性能評価に関して","第31回多値論理とその応用研究会",,,,,,2018,Jan.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","All Binarized Convolutional Neural Network and Its implementation on an FPGA","The International Conference on Field-Programmable Technology (FPT 2017)",,,,,"pp. 291-294",2017,Dec.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Masayuki Shimoda,Shimpei Sato","GUINNESS: A GUI based neural network synthesizer for an FPGA","The 27th International Conference on Field-programmable Logic and Applications (FPL 2017)",,,,,,2017,Sept.
"Masayuki Shimoda","Gap Channel Routing in VLSI Physical Design",,,,,,,,
"Masayuki Shimoda","Gap Channel Routing in VLSI Physical Design",,,,,,,,