"TOSHINORI YAMADA","On Three-Dimensional Layout of Pyramid Networks",,"Proc. IEEE Asia Pacific Conference on Circuits and Systems",,,,,2002,
"TOSHINORI YAMADA","Optimal Fault-Tolerant Linear Arrays",,"Technical Report of IEICE",,"Vol. CAS2002-88",,,2002,
"TOSHINORI YAMADA","On Three-Dimensional Layout of de Bruijn Networks",,"Proc. IEEE International Symposium on Circuits and Systems",,"Vol. III",,"pp. 779-782",2002,
"Kenta HASHIMOTO,Toshinori YAMADA,Shuichi UENO","On-Line Multicasting in All-Optical Networks",,"Lecture Notes in Computer Science (LNCS)",,"Vol. 2223",,"pp. 99-106",2001,
"Tadashi NISHIYAMA,Toshinori YAMADA,Shuichi UENO","On VLSI Decomposition for d-ary deBruijn Graphs",,"Tech. Report of IEICE",,"Vol. COMP2000-70",,"pp. 47-54",2001,
"Toshinori YAMADA,Shuichi UENO","On Three-Dimensional Layout of de Bruijn Networks",,"Tech. Report of IEICE",,"Vol. COMP2001-17",,"pp. 33-40",2001,
"Kumiko NOMURA,Toshinori YAMADA,Shuichi UENO","On Adaptive Fault Diagnosis for Multiprocessor Systems",,"Tech. Report of IEICE",,"Vol. COMP2001-19",,"pp. 49-56",2001,
"Kenta HASHIMOTO,Toshinori YAMADA,Shuichi UENO","On-Line Multicasting in All-Optical Networks",,"Tech. Report of IEICE",,"Vol. COMP2001-20",,"pp. 57-63",2001,
"Toshinori YAMADA,Nobuaki FUJII,Shuichi UENO","On Three-Dimensional Layout of Pyramid Networks",,"Tech. Report of IEICE",,"Vol. CAS2001-75",,"pp. 77-82",2001,
"Kumiko NOMURA,Toshinori YAMADA,Shuichi UENO","On Adaptive Fault Diagnosis for Multiprocessor Systems",,"Lecture Notes in Computer Science (LNCS)",,"Vol. 2223",,"pp. 86-98",2001,
"Toshinori Yamada,Akitsugu Watanabe,Shuichi Ueno","On Sequential Diagnosis of Multiprocessor Systems",,"Tech. Report of IEICE",,"Vol. CAS2000-70",,"pp. 65-72",2000,
"Suguru Amitani,Toshinori Yamada,Shuichi Ueno","Optimal Layouts of Virtual Paths in Complete Binary Tree ATM Networks",,"Tech. Report of IEICE",,"Vol. CAS2000-71",,"pp. 73-78",2000,
"Kumiko Nomura,Toshinori Yamada,Shuichi Ueno","Sparce Networks Tolerating Random Faults for Tree-Like and Butterfly-Like Networks",,"Proc. of 2000 IEEE Asia Pacific Conference on Circuits and Systems",,,,"pp. 799-802",2000,
"Toshinori Yamada,Takashi Mori,Shin-ichiro Tago,Shuichi Ueno","Optimal Implementation of CCC's by Three-Dimensional Space-Invariant Optical Interconnections",,"Proc. of 2000 IEEE Asia Pacific Conference on Circuits and Systems",,,,"pp. 879-882",2000,
"Atsushi Yamazaki,Toshinori Yamada,Shuichi Ueno","On Sequential Diagnosis of Multiprocessor Systems under Probabilistic Models",,"Tech. Report of IEICE",,"Vol. COMP99-70",,"pp. 9-16",2000,
"Yoshiyasu Doi,Toshinori Yamada,Shuichi Ueno","Three-Dimensional VLSI Layouts of de Bruijn and Shuffle-Exchange Networks",,"Tech. Report of IEICE",,"Vol. COMP99-71",,"pp. 17-24",2000,
"Toshinori Yamada,Akitsugu Watanabe,Shuichi Ueno","A Note on Sequential Diagnosis of Multiprocessor Systems",,"Proc. of the 61st National Convension of IPSJ",,"Vol. 1",,"pp. 227-228",2000,
"Kumiko Nomura,Toshinori Yamada,Shuichi Ueno","Sparce Networks Tolerating Random Faults for Tree-Like and Butterfly-Like Networks",,"Proc. of the 61st National Convension of IPSJ",,"Vol. 1",,"pp. 229-230",2000,
"Suguru Amitani,Toshinori Yamada,Shuichi Ueno","Optimal Layouts of Virtual Paths in Complete Binary Tree ATM Networks",,"Proc. of the 61st National Convension of IPSJ",,"Vol. 1",,"pp. 231-232",2000,
"Kumiko Nomura,Toshinori Yamada,Shuichi Ueno","Sparce Networks Tolerating Random Faults for Tree-Like and Butterfly-Like Networks",,"Tech. Report of IEICE",,"Vol. CAS2000-69",,"pp. 59-64",2000,
"Toshinori YAMADA,Shuichi UENO","Sparse Networks Tolerating Random Faults",,"Proc. of 1999 International Symposium on Parallel Architectures, Algorithms and Networks",,,,"pp. 114-118",1999,
"Toshinori YAMADA,Shuichi UENO","On VLSI Decompositions for deBruijn Graphs",,"Proc. of 1999 IEEE International Symposium on Circuits and Systems",,"Vol. VI",,"pp. 165-169",1999,
"Toshinori YAMADA,Shuichi UENO","Fault-Tolerant Graphs for Tori",,"Networks",,"Vol. 32",,"pp. 181-188",1998,
"Toshinori YAMADA,Shuichi UENO","Fault-Tolerant Meshes with Efficient Layouts",,"IEICE Transactions on Information and Systems",,"Vol. E81-D","No. 1","pp. 56-65",1998,
"ŽR“c•q‹K","Fault-Tolerant Networks for Parallel and VLSI Systems",,,,,,,1998,