"Kengo R. Azegami,Masato Inagi,Atsushi Takahashi,Yoji Kajitani","An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm",,"IEICE Trans. Fundamentals",,"Vol. E85-A","No. 3","pp. 655-663",2002,Mar.
"Zhonglin Wu,Shigetoshi Nakatake,Atsushi Takahashi,Yoji Kajitani","Hierarchical BSG floorplan for hierarchical VLSI circuit design",,"Electronics and Communications in Japan (Part III: Fundamental Electronic Science)",,"Vol. 85","No. 3","pp. 12-21",2002,Mar.
"野島隆志,坂主圭史,高橋篤司,梶谷洋司","配線可能性を保証するSequence-Pairを用いた配置手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2001-54)",,"Vol. 101","No. 144","pp. 59-65",2001,June
"Kengo R. Azegami,Atsushi Takahashi,Yoji Kajitani","An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut",,"IEICE Trans. Fundamentals",,"Vol. E84-A","No. 5","pp. 1301-1308",2001,May
"山崎博之,三上直人,高橋篤司,梶谷洋司","モジュールの重なりを許さない力学的モデルによるモジュール配置手法の提案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2000-136)",,"Vol. 100","No. 646","pp. 13-18",2001,Mar.
"呉中林,中武繁寿,高橋篤司,梶谷洋司","VLSI回路の階層設計をサポートする階層化BSGフロアプラン",,"電子情報通信学会論文誌",,"Vol. J83-A","No. 10","pp. 1161-1168",2000,Oct.
"稲木雅人,梶谷洋司,高橋篤司","近接度に着目した入出力ピン配置アルゴリズム",,"電子情報通信学会 基礎・境界ソサイエティ大会 講演論文集 (A-3-1)",,"Vol. A",,"p. 68",2000,Sept.
"野島隆志,梶谷洋司,高橋篤司","局所方向性を持つFPGAの経由スイッチ数最小化配置アルゴリズム",,"電子情報通信学会 基礎・境界ソサイエティ大会 講演論文集 (A-3-4)",,"Vol. A",,"p. 71",2000,Sept.
"Kengo R. Azegami,Atsushi Takahashi,Yoji Kajitani","An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD99-93)",,"Vol. 99","No. 529","pp. 49-56",2000,Jan.
"Yoji Kajitani,Atsushi Takahashi,Shigetoshi Nakatake,Kengo R. Azegami","Partition, Packing and Clock Distribution: A New Paradigm of Physical Design",,"Proc. 13th International Conference on VLSI Design",,,,"p. 29",2000,Jan.
"久保ゆき子,高島康裕,中武繁寿,梶谷洋司","Flipにより自己変換するスタイナ木とそのVLSI最適配線への応用",,"情報処理学会論文誌",,"Vol. 41","No. 4","pp. 881-888",2000,
"K. Sakanushi,Y. Kajitani","The Quarter-State Sequence (Q-Sequence) to Represent the Floorplan and Applications to Layout Optimization",,"Proc. of IEEE Asia Pacific Conference on Circuits and Systems 2000",,,,"pp. 829-832",2000,
"H. Yamazaki,K. Sakanushi,Y. Kajitani","Optimum Packing of Convex-Polygons by A New Data Structure Sequence-Table",,"Proc. of IEEE Asia Pacific Conference on Circuits and Systems 2000",,,,"pp. 821-824",2000,
"Z. Wu,K. Sakanushi,Y. Kajitani","Reuse of VLSI Layout Topology by Parametric BSG",,"Proc. of IEEE Asia Pacific Conference on Circuits and Systems 2000",,,,"pp. 817-820",2000,
"Y. Kubo,Y. Takashima,S. Nakatake,Y. Kajitani","Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout",,"Proc. of Asia and South Pacific Design Automation Conference 2000",,,,"pp. 87-92",2000,
"設楽秀之,畔上健吾,坂主圭史,梶谷洋司","クリティカルパスのリビジットに着目した回路分割遅延改善手法の提案",,"電子情報通信学会技術報告書(VLD99-124)",,"Vol. 99","No. 659","pp. 55-62",2000,
"H. Yamazaki,K. Sakanushi,S. Nakatake,Y. Kajitani","The 3D-Packing by Meta Data Structure and Packing Heuristics",,"IEICE Trans. on Fundamentals",,"Vol. E83-A","No. 4","pp. 639-645",2000,
"坂主 圭史,翠川 賢太郎,梶谷 洋司","Reduct-Seq表現による高速な一般構造フロアプラニング",,"電子情報通信学会技術報告書(CAS2000-15)",,"Vol. 100","No. 118","pp. 109-116",2000,
"坂主 圭史,梶谷 洋司","壁と部屋に関する位相方形分割のReduct-Seqによる数え上げ",,"電子情報通信学会技術報告書(COMP2000-17)",,"Vol. 100","No. 144","pp. 25-32",2000,
"呉 中林,坂主 圭史,梶谷 洋司","パラメトリックBSGによるレイアウトデザインの再利用",,"電子情報通信学会技術報告書(VLD2000-55)",,"Vol. 100","No. 293","pp. 47-52",2000,
"大戸友博,高橋篤司,梶谷洋司","疑似気圧モデルに基づくＶＬＳＩフロアプランの局所修正","システムLSI設計技術研究会","情報処理学会研究報告 (99-SLDM-93)",,"Vol. 99","No. 101","pp. 127-134",1999,Nov.
"Kengo R. Azegami,Atsushi Takahashi,Yoji Kajitani","Enumerating the Min-cut Edges with Applications to Graph Partition under Size Constraints",,"Proc. IEEE International Symposium on Circuits and Systems (ISCAS 1999)",,"Vol. VI",,"pp. 174-177",1999,June
"Tomoyuki Yoda,Atsushi Takahashi,Yoji Kajitani","Clock period minimization of semi-synchronous circuits by gate-level delay insertion",,"Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 1999)",,,,"pp. 125-128",1999,Jan.
"坂主 圭史,山崎 博之,島倉 英規,中武 繁寿,梶谷 洋司","探索的手法に基づく凸多角形パッキング手法の提案",,"電子情報通信学会技術報告書(COMP99-36)",,"Vol. 99","No. 288","pp. 37-44",1999,
"坂主 圭史,中武 繁寿,梶谷 洋司","凸型矩形配置における最適性を保証するBSG解空間の構築",,"第12回 回路とシステム（軽井沢）ワークショップ論文集",,,,"pp. 463-468",1999,
"山崎 博之,坂主 圭史,中武 繁寿,梶谷 洋司","抽象データ構造による高密度3次元パッキング手法",,"電子情報通信学会技術報告書(COMP99-13)",,"Vol. 99","No. 86","pp. 25-32",1999,
"大戸友博,高橋篤司,梶谷洋司","擬似気圧モデルに基づくVLSIフロアプランの局所修正",,"情報処理学会研究報告(99-SLDM-93)",,"Vol. 99","No. 101","pp. 127-134",1999,
"横丸敏彦,高橋篤司,梶谷洋司","マルチプロセッサの低消費電力化のためのクロックON/OFFスケジューリング","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD98-128)",,"Vol. 98","No. 447","pp. 79-85",1998,Dec.
"畔上謙吾,高橋篤司,梶谷洋司","最大フロー手法を応用した論理回路モデルグラフの最小カット列挙法と回路分割手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD98-116)",,"Vol. 98","No. 446","pp. 131-138",1998,Dec.
"Yasuhiro Takashima,Atsushi Takahashi,Yoji Kajitani","Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk",,"IEICE Trans. Fundamentals",,"Vol. E81-A","No. 9","pp. 1909-1915",1998,Sept.
"西川慎哉,高橋篤司,梶谷洋司","準同期式回路の実現に適したクロック木構成法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD98-50,ICD98-153,FTS98-77)",,"Vol. 98","No. 287","pp. 43-50",1998,Sept.
"依田友幸,高橋篤司,梶谷洋司","ゲートレベルの遅延挿入による準同期式回路のクロック周期の最小化",,"DAシンポジウム'98 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 98","No. 9","pp. 233-238",1998,July
"片渕啓太郎,泉知論,高橋篤司,梶谷洋司","リソース制約付き回路分割問題に関する一考察","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD98-35)",,"Vol. 98","No. 232","pp. 33-38",1998,July
"Tomonori Izumi,Toshihiko Yokomaru,Atsushi Takahashi,Yoji Kajitani","Computational Complexity Analysis of Set-Bin-Packing Problem",,"Proc. International Symposium on Circuits And Systems (ISCAS 1998)",,"Vol. 6",,"pp. 244-247",1998,June
"Tomonori Izumi,Toshihiko Yokomaru,Atsushi Takahashi,Yoji Kajitani","Computational Complexity Analysis of Set-Bin-Packing Problem",,"IEICE Trans. Fundamentals",,"Vol. E81-A","No. 5","pp. 842-849",1998,May
"Yasuhiro Takashima,Atsushi Takahashi,Yoji Kajitani","Routability of FPGAs with Extremal Switch-Block Structures",,"IEICE Trans. Fundamentals",,"Vol. E81-A","No. 5","pp. 850-856",1998,May
"Tomonori Izumi,Atsushi Takahashi,Yoji Kajitani","Air-pressure Model and Fast Algorithms for Zero-wasted-area Layout of General Floorplan",,"IEICE Trans. Fundamentals",,"Vol. E81-A","No. 5","pp. 857-865",1998,May
"Kazunori Inoue,Wataru Takahashi,Atsushi Takahashi,Yoji Kajitani","Schedule-Clock-Tree Routing for Semi-Synchronous Circuits","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD97-133,ICD97-238)",,"Vol. 97","No. 577","pp. 79-86",1998,Mar.
"Tomonori Izumi,Atsushi Takahashi,Yoji Kajitani","Air-Pressure-Model-Based Fast Algorithms for General Floorplan",,"Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 1998)",,,,"pp. 563-570",1998,Feb.
"梶谷洋司","配置の数理：多数の長方形を最小面積に埋め込む",,"電子情報通信学会技術研究報告(VLD98-38,ICD98-141,CPSY98-75,FTS98-65)",,"Vol. 98","No. 286","pp. 7-14",1998,
"Keishi SAKANUSHI,Shigetoshi NAKATAKE,Yoji KAJITANI","The Multi-BSG: Stochastic Approach to an Optimum Packing of Convex-Rectilinear Blocks",,"Proc. of International Conference on Computer Aided Design",,,,"pp. 267-274",1998,
"呉中林,中武繁寿,梶谷洋司","高速フロアプラナを実現するBSG階層化技術の提案",,"DAシンポジウム'98論文集",,,,"pp. 25-30",1998,
"坂主圭史,中武繁寿,梶谷洋司","凸型矩形を扱うMultiple-BSG配置手法の提案",,"電子情報通信学会技術研究報告(VLD97-131,ICD97-236)",,"Vol. 97","No. 577","pp. 63-70",1998,
"Shigetoshi NAKATAKE,Yoji KAJITANI,Masahiro FURUYA","Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules",,"Proc. of Asia and South Pacific Design Automation Conference '98",,,,"pp. 571-576",1998,
"Keishi SAKANUSHI,Shigetoshi NAKATAKE,Yoji KAJITANI,Masahiro KAWAKITA","The Channel-BSG: A Universal Floorplan for Simultaneous Place/Route with IC Applications",,"Proc. of International Conference on Computer Aided Design",,,,"pp. 418-425",1998,
"Atsushi Takahashi,Wataru Takahashi,Yoji Kajitani","Clock-Routing Driven Layout Methodology for Semi-Synchronous Circuit Design",,"Proc. 1997 IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)",,,,"pp. 63-66",1997,Dec.
"Atsushi Takahashi,Kazunori Inoue,Yoji Kajitani","Clock-Tree Routing Realizing a Clock-Schedule for Semi-Synchronous Circuits",,"Proc. IEEE/ACM International Conference on Computer Aided Design '97 (ICCAD)",,,,"pp. 260-265",1997,Nov.
"高橋渡,高橋篤司,梶谷洋司","準同期式におけるクロック配線駆動配置手法","設計自動化研究会","情報処理学会研究報告 (97-DA-85)",,"Vol. 97","No. 103","pp. 31-36",1997,Oct.
"三林秀樹,高橋篤司,梶谷洋司","線長の総和と最大に関する均衡平面スタイナー木","設計自動化研究会","情報処理学会研究報告 (97-DA-85)",,"Vol. 97","No. 103","pp. 37-44",1997,Oct.
"泉知論,高橋篤司,梶谷洋司","一般構造フロアプランの面積最小化のための疑似気圧モデルと高速アルゴリズム",,"電子情報通信学会 基礎・境界ソサイエティ大会 講演論文集 (A-3-1)",,"Vol. A",,"p. 53",1997,Sept.
"高橋篤司,井上一紀,森下和明,梶谷洋司","準同期式回路のためのクロック配線および遅延挿入手法",,"電子情報通信学会 基礎・境界ソサイエティ大会 講演論文集 (A-3-14)",,"Vol. A",,"p. 66",1997,Sept.
"泉知論,高橋篤司,梶谷洋司","一般構造フロアプランの面積最小化のための疑似気圧モデルと高速アルゴリズム","VLSI設計技術研究会","電子情報通信学会技術研究報告 (CAS97-41, VLD97-41, DSP97-56)",,"Vol. 97","No. 137","pp. 183-190",1997,June
"Hideki Mitsubayashi,Atsushi Takahashi,Yoji Kajitani","Cost-Radius Balanced Spanning/Steiner Trees",,"IEICE Trans. Fundamentals",,"Vol. E80-A","No. 4","pp. 689-694",1997,Apr.
"高島康裕,高橋篤司,梶谷洋司","総隣接並走距離最小化問題",,"第10回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 421-426",1997,Apr.
"浅中和典,中武繁寿,高橋篤司,梶谷洋司","相似拡大モデルに基づき配線領域を確保したモジュール配置手法の提案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD96-102)",,"Vol. 96","No. 556","pp. 47-54",1997,Mar.
"古屋正浩,中武繁寿,高橋篤司,梶谷洋司","座標固定モジュールを扱うBSG構造におけるモジュール配置手法の考案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD96-103)",,"Vol. 96","No. 556","pp. 55-62",1997,Mar.
"佐々木将央,高橋篤司,梶谷洋司","密度推定に基づく全ネット同時配線手法：端点成長法","設計自動化研究会","情報処理学会研究報告 (97-DA-83)",,"Vol. 97","No. 17","pp. 89-96",1997,Feb.
"井上一紀,高橋篤司,梶谷洋司","スキュー制御クロックネットワークの構成","設計自動化研究会","情報処理学会研究報告 (97-DA-83)",,"Vol. 97","No. 17","pp. 81-88",1997,Feb.
"森下和明,高橋篤司,梶谷洋司","準同期式回路における遅延最適化によるクロック高速化","設計自動化研究会","情報処理学会研究報告 (97-DA-83)",,"Vol. 97","No. 17","pp. 73-80",1997,Feb.
"Atsushi Takahashi,Yoji Kajitani","Performance and Reliability Driven Clock Scheduling of Sequential Logic Circuits",,"Proc. Asia and South Pacific Design Automation Conference '97 (ASP-DAC)",,,,"pp. 37-42",1997,Jan.
"Kunihiro FUJIYOSHI,Yoji KAJITANI,Hiroshi NIITSU","Design of Minimum and Uniform Bipartites for Optimum Connection Blocks of FPGA",,"IEEE Trans. on Computer Aided Design",,"Vol. 16","No. 11","pp. 1377-1383",1997,
"三林秀樹,高橋篤司,梶谷洋司","指定点からの距離制限付き矩形スタイナー木の構成",,"DAシンポジウム'96, 情処シンポジウム論文集, 情報処理学会",,"Vol. 96","No. 4","pp. 195-200",1996,Aug.
"泉知論,横丸敏彦,高橋篤司,梶谷洋司","端子数制約のもとでの回路分割のための集合ビンパッキング問題の一解法",,"第9 回回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 73-78",1996,Apr.
"Yasuhiro Takashima,Atsushi Takahashi,Yoji Kajitani","Detailed-Routability of FPGAs with Extremal Switch-Block Structures",,"Proc. the European Design & Test Conference 1996 (ED&TC)",,,,"pp. 160-164",1996,
"Hideki Mitsubayashi,Atsushi Takahashi,Yoji Kajitani","Cost-Radius Balanced Spanning/Steiner Trees",,"Proc. IEEE Asia Pacific Conference on Circuits and Systems '96 (APCCAS)",,,,"pp. 377-380",1996,
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two",,"IEICE Trans. Fundamentals",,"Vol. E78-A","No. 12","pp. 1828-1839",1995,Dec.
"横丸敏彦,泉知論,高橋篤司,梶谷洋司","容量を固定した整数ビンパッキング問題のFFD法による解法","設計自動化研究会","情報処理学会研究報告 (95-DA-76)",,"Vol. 95","No. 72","pp. 1-8",1995,July
"Atsushi Takahashi,Masahiro Furuya,Yoji Kajitani","Clock Period Minimization by Clock Skew Control","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD95-42)",,"Vol. 95","No. 109","pp. 85-92",1995,June
"高島康裕,高橋篤司,梶谷洋司","配線可能性を保証するFPGAの解析と構成法",,"第8回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 103-108",1995,Apr.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Universal Graphs for Graphs with Bounded Path-Width",,"IEICE Trans. Fundamentals",,"Vol. E78-A","No. 4","pp. 458-462",1995,Apr.
"秋山陽子,高橋篤司,梶谷洋司","強パス遅延テスト可能な論理回路の解析と合成","回路とシステム研究会","電子情報通信学会技術研究報告 (CAS94-124)",,"Vol. 94","No. 530","pp. 25-32",1995,Mar.
"Tomonori Izumi,Toshihiko Yokomaru,Atsushi Takahashi,Yoji Kajitani","Computational Complexity Map of the Set Bin-Packing Problem",,"Proc. IEICE General Conference (A-110)",,"Vol. 1",,"p. 110",1995,Mar.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","On the Proper-Path-Decomposition of Trees",,"IEICE Trans. Fundamentals",,"Vol. E78-A","No. 1","pp. 131-136",1995,Jan.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Mixed-Searching and Proper-Path-Width",,"Theoretical Computer Science",,"Vol. 137","No. 2","pp. 253-268",1995,
"Tomonori Izumi,Toshihiko Yokomaru,Atsushi Takahashi,Yoji Kajitani","Cube-Packing Problem with Fixed Bin-Capacity (>= 3) is NP-complete","Design Automation","IPSJ SIG Technical Reports (94-DA-72)",,"Vol. 94","No. 93","pp. 1-6",1994,Oct.
"石川宏之,高橋篤司,梶谷洋司","セルアレイ方式VLSIのセル行内の相対関係を保存したセルの最適配置に関する研究",,"DAシンポジウム'94, 情処シンポジウム論文集, 情報処理学会",,"Vol. 94","No. 5","pp. 49-54",1994,Aug.
"高島康裕,高橋篤司,梶谷洋司","FPGAのスイッチブロックのアーキテクチャについての研究",,"DAシンポジウム'94, 情処シンポジウム論文集, 情報処理学会",,"Vol. 94","No. 5","pp. 165-170",1994,Aug.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Minimal Acyclic Forbidden Minors for the Family of Graphs with Bounded Path-Width",,"Discrete Mathematics",,"Vol. 127",,"pp. 293-304",1994,
"平賀健文,小関譲,梶谷洋司,高橋篤司","2点間最短路を求める両方向探索アルゴリズムの効率化",,"第6回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 249-254",1993,Apr.
"高橋篤司,上野修一,梶谷洋司","真のパス幅が高々２のグラフの族に対する極小禁止マイナー","回路とシステム研究会","電子情報通信学会技術研究報告 (CAS92-51)",,"Vol. 92","No. 236","pp. 69-76",1992,Sept.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Universal Graphs for Graphs with Bounded Path-Width",,"Proc. 5th Karuizawa Workshop on Circuits and Systems",,,,"pp. 179-184",1992,Apr.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Universal Graphs for Graphs with Bounded Path-Width",,"Proc. IEEE Asia-Pacific Conference on Circuits and Systems '92 (APCCAS)",,,,"pp. 419-423",1992,
"Atsushi Takahashi,Yoji Kajitani","Peel-the-Box: A Concept of Switch-Box Routing and Tractable Problems",,"INTEGRATION, the VLSI journal",,"Vol. 14","No. 1","pp. 33-47",1992,
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Universal Graphs for Graphs with Bounded Path-Width","Algorithms,","IPSJ SIG Technical Reports (91-AL-24-3)",,"Vol. 91","No. 102",,1991,Nov.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","On the Proper-Path-Decomposition of Trees","Technical Committee on Circuits and Systems","IEICE Technical Report (CAS91-74)",,"Vol. 91","No. 255","pp. 23-26",1991,Sept.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Mixed-Searching and Proper-Path-Width","Algorithms","IPSJ SIG Technical Reports (91-AL-22-7)",,"Vol. 91","No. 69",,1991,July
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Mixed-Searching and Proper-Path-Width",,"Proc. 4th Karuizawa Workshop on Circuits and Systems",,,,"pp. 215-220",1991,Apr.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Minimal Acyclic Forbidden Minors for the Family of Graphs with Bounded Path-Width","Algorithms","IPSJ SIG Technical Reports  (91-AL-19-3)",,"Vol. 91","No. 11",,1991,Jan.
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Mixed-Searching and Proper-Path-Width",,"Proc. Second Annual International Symposium on Algorithms, Lecture Notes in Computer Science",,"Vol. 557",,"pp. 61-71",1991,
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","Path-Width and Proper-Path-Width",,"Proc. International Workshop on Graph and Graph Transformations: Tree-structured graphs, forbidden configurations and graph algorithms",,,,"pp. 13-14",1991,
"Atsushi Takahashi,Shuichi Ueno,Yoji Kajitani","A Characterization of the Cycle-Free k-Path in Terms of Forbidden Minors",,"Proc. the Second Japan Conference on Graph Theory and Combinatorics",,,,"p. 42",1990,Aug.
"Atsushi Takahashi,Yoji Kajitani","A Switch-Box Router 'BOX-PEELER' and Its Tractable Problems",,"The Transactions of the IEICE",,"Vol. E72","No. 12","pp. 1367-1373",1989,Dec.
"Atsushi Takahashi,Yoji Kajitani","A Switch-Box Router 'BOX-PEELER' and Its Tractable Problem",,"Proc. 2nd Karuizawa Workshop on Circuits and Systems",,,,"pp. 374-381",1989,May
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