"Yukihide Kohira,Haruki Nakayama,Naoki Nonaka,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","A formulation of mask optimization into QUBO model for Ising machines",,"Proc. SPIE 12751, Photomask Technology 2023, 127511D",,,,,2023,Nov.
"堀本 遊,齊藤颯太,高橋篤司,小平行秀,児玉親亮","振幅成分を利用した補正による忠実度の高いマスクパターン生成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-79)",,"Vol. 122","No. 402","pp. 37-42",2023,Mar.
"齊藤颯太,堀本 遊,高橋篤司,小平行秀,児玉親亮","ボロノイ図を用いたSRAF配置とLUTベース光強度評価による高速SRAF最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-80)",,"Vol. 122","No. 402","pp. 43-48",2023,Mar.
"野中尚貴,小平行秀,高橋篤司,児玉親亮","ボロノイ分割と繰り返し改善によるマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-41)",,"Vol. 122","No. 283","pp. 127-132",2022,Nov.
"小平行秀,中山晴貴,野中尚貴,松井知己,高橋篤司,児玉親亮","シミュレーテッド量子アニーリングを用いたマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2021-45)",,"Vol. 121","No. 277","pp. 162-167",2021,Dec.
"野中尚貴,小平行秀,東梨奈,松井知己,高橋篤司,児玉親亮","勾配判定法と劣勾配法を用いたマスク最適化","第34回 回路とシステムワークショップ","第34回 回路とシステムワークショップ 論文集",,,,"pp. 213-218",2021,Aug.
"Tahsin Shameem,Shimpei Sato,Atsushi Takahashi,Hiroyoshi Tanabe,Yukihide Kohira,Chikaaki Kodama","A Fast LUT Based Point Intensity Computation for OPC Algorithm",,"Proc. the 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2021)",,,,"pp. 92-97",2021,Mar.
"Tahsin Binte Shameem,Atsushi Takahashi,Hiroyoshi Tanabe,Yukihide Kohira,Chikaaki Kodama","A Fast Look Up Table Based Lithography Simulator with SOCS Model for OPC Algorithm",,"Proc. DA Symposium 2020, IPSJ Symposium Series",,,,"pp. 142-149",2020,Sept.
"東梨奈,小平行秀,松井知己,高橋篤司,児玉親亮","ラグランジュ緩和法と境界Flippingによるプロセスばらつきを考慮したピクセルベースマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2019-105)",,"Vol. 119","No. 443","pp. 65-70",2020,Mar.
"Rina Azuma,Yukihide Kohira,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","Process variation-aware mask optimization with iterative improvement by subgradient method and boundary ?ipping",,"Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280O",,,,"pp. 1-7",2020,Mar.
"小平行秀,東梨奈,松井知己,高橋篤司,児玉親亮","劣勾配法によるプロセスばらつきを考慮したマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2019-53)",,"Vol. 119","No. 282","pp. 197-202",2019,Nov.
"東梨奈,小平行秀,松井知己,高橋篤司,児玉親亮,野嶋茂樹","0-1二次計画法によるプロセスばらつきを考慮したモデルベースマスク補正手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2018-70)",,"Vol. 118","No. 334","pp. 209-214",2018,Dec.
"Yukihide Kohira,Atsushi Takahashi,Tomomi Matsui,Chikaaki Kodama,Shigeki Nojima,Satoshi Tanaka","Manufacturability-aware Mask Assignment in Multiple Patterning Lithography",,"Proc. the 2016 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2016)",,,,"pp. 538-541",2016,Oct.
"Yukihide Kohira,Chikaaki Kodama,Tomomi Matsui,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process",,"Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3)",,"Vol. 15","No. 2","pp. 1-7",2016,Mar.
"小平行秀,児玉親亮,松井知己,高橋篤司,野嶋茂樹,田中聡","マスク位置ずれに対する耐性を持つLELECUTトリプルパターニングのためのマスク割り当て手法",,"次世代リソグラフィワークショップ予稿集 (NGL2015)",,,,"pp. 35-36",2015,July
"Yukihide Kohira,Chikaaki Kodama,Tomomi Matsui,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware mask assignment using positive semidefinite relaxation in LELECUT triple patterning",,"Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270B",,,,"  1-9",2015,Mar.
"Yukihide Kohira,Tomomi Matsui,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Fast Mask Assignment using Positive Semidefinite Relaxation in LELECUT Triple Patterning Lithography",,"Proc. Asia and South Pacific Design Automation Conference 2015 (ASP-DAC 2015)",,,,"pp. 665-670",2015,Jan.
"Yukihide Kohira,Atsushi Takahashi","2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E97-A","No. 12","pp. 2459-2466",2014,Dec.
"Atsushi Takahashi,Ahmed Awad,Yukihide Kohira,Tomomi Matsui,Chikaaki Kodama,Shigeki Nojima,Satoshi Tanaka","[Invited] Multi Patterning Techniques for Manufacturability Enhancement in Optical Lithography",,"Proc. the 2014 International Conference on Integrated Circuits, Design, and Verification (ICDV 2014)",,,,"pp. 117-122",2014,Nov.
"Tomomi Matsui,Yukihide Kohira,Chikaaki Kodama,Atsushi Takahashi","Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography","the 25th International Symposium on Algorithms and Computation (ISAAC 2014)","Algorithms and Computation, Lecture Notes in Computer Science",,"  LNCS 8889",,"pp. 365?375",2014,Nov.
"小平行秀,横山陽子,児玉親亮,高橋篤司,野嶋茂樹,田中聡","LELEダブルパターニングのための歩留まりを考慮した高速マスク割り当て手法",,"次世代リソグラフィワークショップ予稿集 (NGL2014)",,,,"pp. 41-42",2014,July
"小平行秀,松井知己,横山陽子,児玉親亮,高橋篤司,野嶋茂樹,田中聡","半正定値緩和法を用いたLELECUTトリプルパターニングのためのレイアウト分割手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2014-6)",,"Vol. 114","No. 59","pp. 27-32",2014,May
"宮辺祐太郎,高橋篤司,松井知己,小平行秀,横山陽子","ダブルパターニングにおけるリソグラフィECOのためのパターン局所修正法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2013-149)",,"Vol. 113","No. 454","pp. 87-92",2014,Mar.
"Yukihide Kohira,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware decomposition for LELE double patterning",,"Proc. SPIE   9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530T",,,,"  1-10",2014,Mar.
"Yoko Yokoyama,Keishi Sakanushi,Yukihide Kohira,Atsushi Takahashi,Chikaaki Kodama,Satoshi Tanaka,Shigeki Nojima","Localization concept of re-decomposition area to fix hotspots for LELE process",,"Proc. SPIE   9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530V",,,,"  1-8",2014,Mar.
"Yukihide Kohira,Atsushi Takahashi","2-SAT based Linear Time Optimum Two-Domain Clock Skew Scheduling",,"Proc. Asia and South Pacific Design Automation Conference 2014 (ASP-DAC 2014)",,,,"pp. 173-178",2014,Jan.
"Yukihide Kohira,Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Overlap Area Maximization in Stitch Selection for LELE Double Patterning",,"Proc. the 26th Workshop on Circuits and Systems",,,,"pp. 466-471",2013,July
"Yukihide Kohira,Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Minimum Cost Stitch Selection in LELE Double Patterning","Design for Manufacturability and Yield 2013 (DFM&Y2013)",,,,,,2013,June
"Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Yukihide Kohira,Satoshi Tanaka,Keishi Sakanushi,Jiro Higuchi,Shigeki Nojima","A Study of Robust Stitch Design for Litho-etch-litho-etch Double Patterning","Design for Manufacturability and Yield 2013 (DFM&Y2013)",,,,,,2013,June
"小平行秀,高橋篤司","一般同期方式における最適2クラスタ分割手法",,"第25回 回路とシステムワークショップ論文集",,,,"pp. 178-183",2012,July
"篠田享佑,小平行秀,高橋篤司","単層プリント基板のための各ネットの配線長達成性を考慮した等長配線手法",,"電子情報通信学会 2012年総合大会 講演論文集 (A-3-3)",,"Vol. A",,"p. 87",2012,Mar.
"Yukihide Kohira,Atsushi Takahashi","An Any-Angle Routing Method using Quasi-Newton Method",,"Proc. Asia and South Pacific Design Automation Conference 2012 (ASP-DAC 2012)",,,,"pp. 145-150",2012,Jan.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","Single-Layer Trunk Routing Using Minimal 45-Degree Lines",,"IEICE Trans. Fundamentals",,"Vol. E94-A","No. 12","pp. 2510-2518",2011,Dec.
"小平行秀,高橋篤司","準ニュートン法を用いた自由角度配線のための逐次改善手法",,"電子情報通信学会 2011年ソサイエティ大会 講演論文集 (A-3-20)",,"Vol. A",,"p. 94",2011,Sept.
"小平行秀,高橋篤司","準ニュートン法を用いた自由角度配線手法",,"第24回 回路とシステムワークショップ 論文集",,,,"pp. 425-430",2011,Aug.
"Yukihide Kohira,Atsushi Takahashi","CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles",,"IEICE Trans. Fundamentals",,"Vol. E93-A","No. 12","pp. 2380-2388",2010,Dec.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","Single-Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing",,"Proc. the 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010)",,,,"pp. 278-283",2010,Oct.
"小平行秀,高橋篤司","一般同期方式におけるクラスタ分割に基づくクロック木の性能評価",,"電子情報通信学会 2010ソサイエティ大会 講演論文集 (A-3-1)",,"Vol. A",,"p. 63",2010,Sept.
"篠田享佑,小平行秀,高橋篤司","単層プリント基板配線のための高混雑度領域特定手法",,"電子情報通信学会 2010ソサイエティ大会 講演論文集 (A-3-4)",,"Vol. A",,"p. 66",2010,Sept.
"小平行秀,高橋篤司","［招待講演］PCB配線設計のための一層複線指定長配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-47)",,"Vol. 110","No. 210","pp. 31-36",2010,Sept.
"篠田享佑,小平行秀,高橋篤司","単層プリント基板配線のための効率的な高混雑度領域特定および45度線による混雑度緩和法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-9)",,"Vol. 110","No. 36","pp. 79-84",2010,May
"小平行秀,高橋篤司","一般同期方式における消費電力を抑えたクロック木構成のためのクラスタ分割法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-119)",,"Vol. 109","No. 462","pp. 121-126",2010,Mar.
"高橋伸嘉,富岡洋一,小平行秀,高橋篤司","入力ベクトルと回路の内部状態を考慮したピーク電力高速見積もり手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-115)",,"Vol. 109","No. 462","pp. 97-102",2010,Mar.
"Yukihide Kohira,Atsushi Takahashi","CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles",,"Proc. Asia and South Pacific Design Automation Conference 2010 (ASP-DAC 2010)",,,,"pp. 281-286",2010,Jan.
"Yoichi Tomioka,Yoshiaki Kurata,Yukihide Kohira,Atsushi Takahashi","MILP-based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 12","pp. 2998-3006",2009,Dec.
"Yukihide Kohira,Suguru Suehiro,Atsushi Takahashi","A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 12","pp. 2971-2978",2009,Dec.
"小平行秀,高橋篤司","障害物を含む1層配線領域のための領域分割によるリバー配線手法",,"電子情報通信学会 2009ソサイエティ大会 講演論文集 (A-3-9)",,"Vol. A",,"p. 58",2009,Sept.
"小平行秀,高橋篤司","1層複線配線問題における幹配線を生成するための壁生成法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-31)",,"Vol. 109","No. 201","pp. 13-18",2009,Sept.
"高橋伸嘉,富岡洋一,小平行秀,高橋篤司","入力ベクトルの適切な選択によるピーク電力高速見積り手法",,"DAシンポジウム2009論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2009","No. 7","pp. 13-18",2009,Aug.
"篠田享佑,小平行秀,高橋篤司","プリント基板のための45度線による混雑度緩和を利用した配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-23,CAS2009-18,SIP2009-35)",,"Vol. 109","No. 111","pp. 97-102",2009,July
"井上雅文,富岡洋一,小平行秀,高橋篤司","パス長制限付き点集合に対する配線木構成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-4)",,"Vol. 109","No. 34","pp. 31-36",2009,May
"Yukihide Kohira,Shuhei Tani,Atsushi Takahashi","Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 4","pp. 1106-1114",2009,Apr.
"Yoshiaki Kurata,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages",,"Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)",,,,"pp. 307-312",2009,Mar.
"末廣傑,小平行秀,高橋篤司","障害物を含む配線領域における並走配線最長化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-137)",,"Vol. 108","No. 487","pp. 59-64",2009,Mar.
"谷修平,小平行秀,高橋篤司","クロック周期短縮のための挿入遅延量を抑えた回路への遅延挿入法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-135)",,"Vol. 108","No. 487","pp. 53-58",2009,Mar.
"橋本浩良,小平行秀,高橋篤司","EDAツールを用いた低コスト一般同期クロックツリー合成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-134)",,"Vol. 108","No. 487","pp. 47-52",2009,Mar.
"Shun Gokita,Yukihide Kohira,Atsushi Takahashi","A Fast Approximation Method of Maximum Operation in Statistical Static Timing Analysis for Achieving Specified Yield",,"Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)",,,,"pp. 364-369",2009,Mar.
"Yukihide Kohira,Suguru Suehiro,Atsushi Takahashi","A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound",,"Proc. Asia and South Pacific Design Automation Conference 2009 (ASP-DAC 2009)",,,,"pp. 600-605",2009,Jan.
"Yukihide Kohira,Shuhei Tani,Atsushi Takahashi","Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework",,"Proc. the 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2008)",,,,"pp. 1680-1683",2008,Dec.
"Yosuke Takahashi,Yukihide Kohira,Atsushi Takahashi","A Fast Clock Scheduling for Peak Power Reduction in LSI",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 12","pp. 3803-3811",2008,Dec.
"小平行秀,高橋篤司","CAFE router: 障害物を含む領域における連結度を考慮した複線配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-72,DC2008-40)",,"Vol. 108","No. 298","pp. 73-78",2008,Nov.
"Yukihide Kohira,Atsushi Takahashi","A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 10","pp. 3030-3037",2008,Oct.
"倉田芳明,富岡洋一,小平行秀,高橋篤司","最近傍ビア配置に基づく2層BGAパッケージ自動配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-55)",,"Vol. 108","No. 224","pp. 49-54",2008,Sept.
"五木田駿,小平行秀,高橋篤司","統計的静的遅延解析における回路の指定歩留まりを達成する最大値見積もり手法",,"DAシンポジウム2008論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2008","No. 7","pp. 193-198",2008,Aug.
"小平行秀,谷修平,高橋篤司","遅延挿入量最小化のためのクロックスケジューリングと遅延挿入手法",,"第21回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 629-634",2008,Apr.
"小平行秀,末廣傑,高橋篤司","障害物を含む領域における連結度を考慮した配線長見積もりを用いた最長配線手法",,"第21回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 569-574",2008,Apr.
"石田勉,小平行秀,高橋篤司","最短パス木修正アルゴリズムの設計とその性能評価","回路とシステム研究会","電子情報通信学会技術研究報告 (CAS2007-98)",,"Vol. 107","No. 476","pp. 25-30",2008,Feb.
"末廣傑,小平行秀,高橋篤司","障害物を含む領域における最大配線長見積もりに関する考察","回路とシステム研究会","電子情報通信学会技術研究報告 (CAS2007-97)",,"Vol. 107","No. 476","pp. 19-23",2008,Feb.
"小平行秀,高橋篤司","一般同期方式向けレジスタ再配置手法の性能評価",,"DAシンポジウム2007 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2007","No. 7","pp. 193-198",2007,Aug.
"橋本浩良,小平行秀,高橋篤司","CADツールを用いた一般同期向けクロック木合成法の改良",,"DAシンポジウム2007 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2007","No. 7","pp. 199-204",2007,Aug.
"古屋宏基,小平行秀,高橋篤司","統計的静的遅延解析による指定良品率を達成する最大遅延値見積もり手法","システムLSI設計技術研究会","情報処理学会研究報告 (2007-SLDM-130)",,"Vol. 2007","No. 39","pp. 75-79",2007,May
"Yukihide Kohira,Atsushi Takahashi","A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework",,"Proc. the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)",,,,"pp. 1795-1798",2007,May
"Yukihide Kohira,Atsushi Takahashi","Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization",,"IEICE Trans. Fundamentals",,"Vol. E90-A","No. 4","pp. 800-807",2007,Apr.
"原田陽介,橋本浩良,小平行秀,高橋篤司","CADツールを用いた一般同期向けクロック木の一合成法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2006-127)",,"Vol. 106","No. 548","pp. 49-53",2007,Mar.
"Yosuke Takahashi,Yukihide Kohira,Atsushi Takahashi","A Fast Clock Scheduling for Peak Power Reduction in LSI",,"Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI 2007)",,,,"pp. 582-587",2007,Mar.
"Yukihide Kohira,Atsushi Takahashi","A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-70)",,"Vol. 106","No. 388","pp. 33-38",2006,Nov.
"石田勉,小平行秀,高橋篤司","負閉路探索手法の性能評価","アルゴリズム研究会","情報処理学会研究報告 (2006-AL-107)",,"Vol. 2006","No. 71","pp. 45-50",2006,July
"Yukihide Kohira,Chikaaki Kodama,Kunihiro Fujiyoshi,Atsushi Takahashi","Evaluation of 3D-Packing Representations for Scheduling of Dynamically Reconfigurable Systems",,"Proc. the 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)",,,,"pp. 4487-4490",2006,May
"Yukihide Kohira,Atsushi Takahashi","Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework",,"Proc. the 13th Workshop on Synthesis And System integration of Mixed Information technologies (SASIMI 2006)",,,,"pp. 134-140",2006,Apr.
"小平行秀,高橋篤司","レジスタの再配置による準同期式回路のクロック周期最小化手法",,"第19回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 259-264",2006,Apr.
"Yukihide Kohira,Atsushi Takahashi","Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework",,"Proc. the 2006 IEICE General Conference (A-3-4)",,"Vol. A",,"p. 68",2006,Mar.
"砂走裕一,小平行秀,高橋篤司","クラスタ分割を用いたスケジューリング法の効率化","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2005-113)",,"Vol. 105","No. 644","pp. 31-36",2006,Mar.
"小平行秀,児玉親亮,藤吉邦洋,高橋篤司","計算資源割り当てスケジューリングのための直方体パッキング表現手法の検討",,"第18回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 211-216",2005,Apr.
"Yukihide Kohira,Atsushi Takahashi","Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion",,"IEICE Trans. Fundamentals",,"Vol. E88-A","No. 4","pp. 892-898",2005,Apr.
"上林英悟,小平行秀,高橋篤司","準同期方式におけるリタイミングを用いた回路修正手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2004-146)",,"Vol. 104","No. 709","pp. 55-60",2005,Mar.
"Yukihide Kohira,Atsushi Takahashi","Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion",,"Proc. the 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004)",,,,"pp. 533-536",2004,Dec.
"小平行秀,児玉親亮,藤吉邦洋,高橋篤司","動的再構成可能なシステムのための計算資源割り当てスケジューリング手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2004-67)",,"Vol. 104","No. 478","pp. 37-42",2004,Dec.
"小平行秀,高橋篤司","遅延挿入による準同期式回路のクロック周期最小化手法",,"第17回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 529-534",2004,Apr.