"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Pre-training CNN for fast EUV lithography simulation including M3D effects",,"Proc. SPIE 12954, DTCO and Computational Patterning III, 129540I","Society of Photo-Optical Instrumentation Engineers (SPIE)",,,,2024,Apr.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP",,"Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024)",,,,"pp. 50-55",2024,Mar.
"Zuan Jiyo,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2023-102)",,"Vol. 123","No. 390","pp. 18-23",2024,Feb.
"Zezhong Wang,Masayuki Shimoda,Atsushi Takahashi","Single Trunk Routing Problem for Generalized Channel","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2023-104)",,"Vol. 123","No. 390","pp. 30-35",2024,Feb.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi TAKAHASHI,モロンゴ マチュー,Makoto Minami,西岡克也","Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2023-103)",,"Vol. 123","No. 390","pp. 24-29",2024,Feb.
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Accelerating extreme ultraviolet lithography simulation with weakly guiding approximation and source position dependent transmission cross coefficient formula",,"Journal of Micro/Nanopatterning, Materials, and Metrology",,"Vol. 23","Issue 1","  014201",2024,Jan.
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Accelerating EUV lithography simulation with weakly guiding approximation and STCC formula",,"Proc. SPIE 12750, International Conference on Extreme Ultraviolet Lithography 2023, 127500D","Society of Photo-Optical Instrumentation Engineers (SPIE)",,,,2023,Nov.
"Yukihide Kohira,Haruki Nakayama,Naoki Nonaka,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","A formulation of mask optimization into QUBO model for Ising machines",,"Proc. SPIE 12751, Photomask Technology 2023, 127511D",,,,,2023,Nov.
"Zuan Jo,Satoshi Tayu,Atsushi Takahashi,Molongo Mathieu,Makoto Minami,Katsuya Nishioka","Pair Symmetrical Routing in Common Centroid Placement with Double Via Constraints",,"Proc. DA Symposium 2023, IPSJ Symposium Series",,,,"pp. 207-212",2023,Aug.
"Onjira Duongthipthewa,Koonlachat Meesublak,Atsushi Takahashi,Chowarit Mitsantisuk","Detection Welding Performance of Industrial Robot Using Machine Learning",,"Proc. International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)",,,,,2023,Aug.
"Katsuharu Yamamoto,Akira Jinguji,Atsushi Takahashi","Droplet routing algorithm for MEDA-based DMFB",,"Proc. DA Symposium 2023, IPSJ Symposium Series",,,,"pp. 173-179",2023,Aug.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Molongo Mathieu,Makoto Minami,Katsuya Nishioka","Three-layer Bottleneck Channel Track Assignment by ILP",,"Proc. DA Symposium 2023, IPSJ Symposium Series",,,,"pp. 199-206",2023,Aug.
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Evaluation of convolutional neural network for fast extreme ultraviolet lithography simulation using imec 3 nm node mask patterns",,"Journal of Micro/Nanopatterning, Materials and Metrology (JM3)","Society of Photo-optical Instrumentation Engineers","Vol. 22","Issue 2","  024201",2023,June
"Atsushi Takahashi","Report on the 28th Asia and South Pacific Design Automation Conference",,"IEEE Design & Test",,"vol. 40","issue 3","pp. 62-63",2023,Apr.
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Evaluation of CNN for fast EUV lithography simulation using iN3 logic mask patterns",,"Proc. SPIE 12495, Advanced Lithography + Patterning 2023, 124951J",,,,,2023,Apr.
"Zuan Jo,Satoshi Tayu,Atsushi Takahashi,Molongo Mathieu,Makoto Minami,Katsuya Nishioka","Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2022-102)",,"Vol. 122","No. 402","pp. 155-160",2023,Mar.
"Yu Horimoto,Sota Saito,Atsushi Takahashi,Yukihide Kohira,Chikaaki Kodama","High fidelity mask pattern generation method by amplitude component evaluation","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2022-79)",,"Vol. 122","No. 402","pp. 37-42",2023,Mar.
"Sota Saito,Yu Horimoto,Atsushi Takahashi,Yukihide Kohira,Chikaaki Kodama","A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2022-80)",,"Vol. 122","No. 402","pp. 43-48",2023,Mar.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Molongo Mathieu,Makoto Minami,Katsuya Nishioka","Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2022-101)",,"Vol. 122","No. 402","pp. 149-154",2023,Mar.
"Surachai Rodsai,Anusorn Iamrurksiri,Chowarit Mitsantisuk,Atsushi Takahashi","Point Cloud Based Guidance for Autonomous Mobile Robot in Sugarcane Plantation",,"Proc. International Symposium on Instrumentation, Control, Artificial Intelligence, and Robotics (ICA-SYMP)",,,,"pp. 15-18",2023,Feb.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 16",,,2023,Feb.
"Atsushi Takahashi","Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023","ASPDAC '23: 28th Asia and South Pacific Design Automation Conference",,,,,,2023,Jan.
"Naoki Nonaka,Yukihide Kohira,Atsushi Takahashi,Chikaaki Kodama","Mask Optimization Using Voronoi Partition and Iterative Improvement","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2022-41)",,"Vol. 122","No. 283","pp. 127-132",2022,Nov.
"Sota Saito,Atsushi TAKAHASHI","A fast SRAF optimization used LUT based intensity estimation","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2022-40)",,"Vol. 122","No. 283","pp. 121-126",2022,Nov.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Yukichi Todoroki,Makoto Minami","Bottleneck Channel Routing to Reduce the Area of Analog VLSI",,"Proc. the 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2022)",,,,"pp. 26-31",2022,Oct.
"Hiroyoshi Tanabe,Atsushi Takahashi","Data augmentation in extreme ultraviolet lithography simulation using convolutional neural network",,"Journal of Micro/Nanopatterning, Materials and Metrology (JM3)",,"Vol. 21","Issue 4","  041602",2022,Oct.
"Zuan Jo,Atsushi Takahashi,Yukichi Todoroki,Makoto Minami","Pair Symmetrical Routing in Common Centroid Placement",,"Proc. DA Symposium 2022, IPSJ Symposium Series",,,,"pp. 21-26",2022,Aug.
"Hiroyoshi Tanabe,Atsushi Takahashi","Data augmentation in EUV lithography simulation based on convolutional neural network","Proc. SPIE 12052, Advanced Lithography + Patterning 2022, 120520T",,,,,,2022,May
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Yukichi Todoroki,Makoto Minami","Bottleneck Channel Routing to Reduce the Area of Analog VLSI","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2021-77)",,"Vol. 121","No. 412","pp. 7-12",2022,Mar.
"Atsushi Takahashi","Take More Return than Give",,"The journal of the Institute of Electronics, Information and Communication Engineers",,"Vol. 105","No. 3",,2022,Mar.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 15",,,2022,Feb.
"Yukihide Kohira,Haruki Nakayama,Naoki Nonaka,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","Mask Optimization Method Using Simulated Quantum Annealing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2021-45)",,"Vol. 121","No. 277","pp. 162-167",2021,Dec.
"Hiroyoshi Tanabe,Shimpei Sato,Atsushi Takahashi","Fast EUV lithography simulation using convolutional neural network",,"Journal of Micro/Nanopatterning, Materials and Metrology (JM3)",,"Vol. 20","No. 4","pp. 1-14",2021,Sept.
"Naoki Nonaka,Yukihide Kohira,Rina Azuma,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","Acceleration of Mask Optimization Using Gradient Deciding Method and Subgradient Method","The 34th Workshop on Circuits and Systems","Proc. the 34th Workshop on Circuits and Systems",,,,"pp. 213-218",2021,Aug.
"Yuta Ukon,Shimpei Sato,Atsushi Takahashi","Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism",,"IEICE Transactions on Electronics",,"Vol. E104-C","No. 7","pp. 309-318",2021,July
"Atsushi Takahashi","What I think as the president of ESS",,"IEICE ESS Fundamentals Review",,"Vol. 15","No. 1",,2021,July
"Tahsin Shameem,Shimpei Sato,Atsushi Takahashi,Hiroyoshi Tanabe,Yukihide Kohira,Chikaaki Kodama","A Fast LUT Based Point Intensity Computation for OPC Algorithm",,"Proc. the 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2021)",,,,"pp. 92-97",2021,Mar.
"Hiroyoshi Tanabe,Shimpei Sato,Atsushi Takahashi","Fast 3D lithography simulation by convolutional neural network",,"Proc. SPIE 11614, Design-Process-Technology Co-optimization XV 2021, 116140M",,,,"pp. 1-8",2021,Feb.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 14",,,2021,Feb.
"Hiroyoshi Tanabe,Shimpei Sato,Atsushi Takahashi","Fast 3D lithography simulation by convolutional neural network: POC study",,"Proc. SPIE 11518, Photomask Technology 2020, 115180L",,,,,2020,Sept.
"Tahsin Binte Shameem,Atsushi Takahashi,Hiroyoshi Tanabe,Yukihide Kohira,Chikaaki Kodama","A Fast Look Up Table Based Lithography Simulator with SOCS Model for OPC Algorithm",,"Proc. DA Symposium 2020, IPSJ Symposium Series",,,,"pp. 142-149",2020,Sept.
"Shimpei Sato,Kano Akagi,Atsushi Takahashi","A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E103-A","No. 9","pp. 1037-1044",2020,Sept.
"Rina Azuma,Yukihide Kohira,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","Pixel-based Mask Optimization with Lagrangian Relaxation and Boundary Flipping","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2019-105)",,"Vol. 119","No. 443","pp. 65-70",2020,Mar.
"Rina Azuma,Yukihide Kohira,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","Process variation-aware mask optimization with iterative improvement by subgradient method and boundary ?ipping",,"Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280O",,,,"pp. 1-7",2020,Mar.
"Hidekazu Takahashi,Hiroki Ogura,Shimpei Sato,Atsushi Takahashi,Chikaaki Kodama","A feature selection method for weak classifier based hotspot detection",,"Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113281E",,,,"pp. 1-7",2020,Mar.
"Kunihiko Wada,Shimpei Sato,Atsushi Takahashi","A Pin-Pair Routing Method for Length Difference Reduction in Set-Pair Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2019-95)",,"Vol. 119","No. 443","pp. 7-12",2020,Mar.
"Hidekazu Takahashi,Shimpei Sato,Atsushi Takahashi","Machine Learning Based Lithography Hotspot Detection Method and Evaluation","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2019-106)",,"Vol. 119","No. 443","pp. 71-76",2020,Mar.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 13",,,2020,Feb.
"Pathawee Phonwiphat,Warut Pannakkong,Pisal Yenradee,Kittipong Ekkachai,Atsushi Takahashi","An Intelligent System for Identifying Feasible Routes for Truck Routing Problem: An Application to a Thai Adhesive and Sealant Company (ATASC)",,"Proc. International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)",,,,"pp. 905-910",2020,Jan.
"Shimpei Sato,Eijiro Sassa,Yuta Ukon,Atsushi Takahashi","A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E102-A","No. 12","pp. 1760-1769",2019,Dec.
"Hiroki Ogura,Hidekazu Takahashi,Shimpei Sato,Atsushi Takahashi","Analysis of databases used for hot spot test cases",,"Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2019-52)",,"Vol. 119","No. 282","pp. 191-196",2019,Nov.
"Yukihide Kohira,Rina Azuma,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","Mask Optimization Considering Process Variation by Subgradient Method","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2019-53)",,"Vol. 119","No. 282","pp. 197-202",2019,Nov.
"Kunihiko Wada,Mayu Owada,Katsuharu Yamamoto,Yu Horimoto,Shimpei Sato,Atsushi TAKAHASHI","グラフの位相埋め込みの配置配線パズルへの適用に関する一検討",,"System LSI Design Methodology, IPSJ SIG Technical Reports",,"Vol. 2019-SLDM-189","No. 31","pp. 1-6",2019,Nov.
"Hidekazu Takahashi,Shimpei Sato,Atsushi Takahashi","A Fast Hotspot Detector Based on Local Features Using Concentric Circle Area Sampling",,"Proc. the 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2019)",,,,"pp. 316-321",2019,Oct.
"Atsushi Takahashi,Hidekazu Takahashi,Hiroki Ogura,Shimpei Sato","Hotspot Detection Methods and their Evaluation in Advanced Lithography",,"Proc. the 16th International SoC Design Conference (ISOCC '19)",,,,"p. 121",2019,Oct.
"Hidekazu Takahashi,Shimpei Sato,Atsushi TAKAHASHI","CCASを用いた局所特徴量に基づくリソグラフィホットスポット検出器の検討",,"Proc. DA Symposium 2019, IPSJ Symposium Series",,,,"pp. 99-104",2019,Aug.
"Shimpei Sato,Eijiro Sassa,Yuta Ukon,Atsushi Takahashi","A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution",,"Proc. IEEE International Symposium on Circuits and Systems (ISCAS '19)",,,,,2019,May
"Pruttapon Maolanon,Kanjanapan Sukvichai,Nattapon Chayopitak,Atsushi Takahashi","Indoor Room Identify and Mapping with Virtual based SLAM using Furnitures and Household Objects Relationship based on CNNs",,"Proc. International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES)",,,,,2019,Apr.
"Atsushi Takahashi","Applications of Discrete Mathematics",,"IEICE B-plus",,,"No. 48","pp. 289-292",2019,Mar.
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","Set-Pair Routing Algorithm with Selective Pin-Pair Connections",,"Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2018-99)",,"vol. 118","no. 457","pp. 37-42",2019,Feb.
"Eijiro Sassa,Shimpei Sato,Atsushi Takahashi","On Delay Optimization for Improving General Synchronous Performance",,"Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2018-72)",,"vol. 118","no. 430","pp. 1-6",2019,Jan.
"Rina Azuma,Yukihide Kohira,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama,Shigeki Nojima","Process Variation-aware Model-based OPC using 0-1 Quadratic Programming","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2018-70)",,"Vol. 118","No. 334","pp. 209-214",2018,Dec.
"Mayu Owada,Kunihiko Wada,Kano Akagi,Shimpei Sato,Atsushi Takahashi","集合対間配線問題ソルバと引きはがし再配線のADC2018問題への適用",,"System LSI Design Methodology, IPSJ SIG Technical Reports",,"Vol. 2018-SLDM-185","No. 13","pp. 1-6",2018,Dec.
"Kano Akagi,Mayu Owada,Kunihiko Wada,Shimpei Sato,Atsushi Takahashi","集合対間配線手法のADC2018への適用に関する一考察",,"System LSI Design Methodology, IPSJ SIG Technical Reports",,"Vol. 2018-SLDM-185","No. 12","pp. 1-6",2018,Dec.
"Kunihiko Wada,Mayu Owada,Kano Akagi,Shimpei Sato,Atsushi Takahashi","ADC2018問題の自動生成手法に関する一検討",,"System LSI Design Methodology, IPSJ SIG Technical Reports",,"Vol. 2018-SLDM-185","No. 11","pp. 1-4",2018,Dec.
"Akinori NISHIHARA,Yuji KAGOHASHI,David STEWART,Atsushi TAKAHASHI,Akira YAMADA","Survey of 6-University Engineering Assistant Professors","The 34th Annual Conference of JSET","Proceedings of the annual conference of JSET","Japan Society for Educational Technology","Vol. 34",,"pp. 853-854",2018,Sept.
"Hidekazu Takahashi,Shimpei Sato,Atsushi Takahashi","Considering low-dimension features based HOG for Human Recognition","DA Symposium 2018","Proc. DA Symposium 2018, IPSJ Symposium Series","Information Processing Society of Japan","Vol. 2018",,"pp. 45-50",2018,Aug.
"Atsushi Takahashi,Shimpei Sato,Hiroki Ogura,Yu-Min Sung,Ting-Chi Wang","Pattern Similarity Metrics for Layout Pattern Classification and their Validity Analysis by Lithographic Responses",,"Proc. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)",,,,"pp. 494-497",2018,July
"Atsushi Takahashi","Routing Algorithms for VLSI and their Theoretical Background","11th International Conference on Embedded Systems and Intelligent Technology (ICESIT 2018) - The Ninth International Conference on Information and Communication Technology for Embedded Systems (IC-ICTES 2018)",,,,,,2018,May
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing",,"Proc. the 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018)",,,,"pp. 337-342",2018,Mar.
"Atsushi Takahashi","Routing Algorithms - from classic to advanced -","IEEE CASS Central China Workshop",,,,,,2017,Nov.
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","A Study on Target Pin-Pairs Selection for Set-Pair Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2017-59)",,"Vol. 117","No. 273","pp. 235-240",2017,Nov.
"Atsushi Takahashi","FR and Fundam Review",,"IEICE ESS Fundamentals Review",,"Vol. 11","No. 2",,2017,Oct.
"Akinori NISHIHARA,David STEWART,Yuji KAGOHASHI,Atsushi TAKAHASHI,Akira YAMADA","Six-University Human Assets Promotion Program for Innovative Education and Research (6U-HAPPIER)","33rd Annual Conference of JSET","Proceedings of the 33rd Annual Conference of JSET",,,,,2017,Sept.
"Atsushi Takahashi","Routing Algorithms - from classic to advanced -","2017 Taiwan and Japan Conference on Circuits and Systems (TJCAS)",,,,,,2017,Aug.
"Takeshi Ihara,Toshiyuki Hongo,Atsushi Takahashi,Chikaaki Kodama","A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E100-A","No. 7","pp. 1473-1480",2017,July
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","An Idea for Maximizing Target Pin-Pair Connections in Set-Pair Routing",,"Proc. the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017)",,,,"pp. 62-65",2017,July
"Yuta Ukon,Shimpei Sato,Atsushi Takahashi","Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2017-26)",,"Vol. 117","No. 97","pp. 119-124",2017,June
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","A Set-Pair Routing Algorithm Realizing Target Pin-Pair Connections","The 30th Workshop on Circuits and Systems","Proc. the 30th Workshop on Circuits and Systems",,,,"pp. 180-185",2017,May
"Atsushi Takahashi","Launch of IEEE CEDA All Japan Joint Chapter and Its Role","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2017-59)",,"Vol. 117","No. 17","pp. 31-34",2017,May
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling",,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems",,"Vol. 25","No. 3","pp. 998-1011",2017,Mar.
"Shun Sugihara,Shimpei Sato,Atsushi Takahashi","Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2016-114)",,"Vol. 116","No. 478","pp. 73-78",2017,Mar.
"Atsushi Ogashira,Shimpei Sato,Atsushi Takahashi","Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2016-113)",,"Vol. 116","No. 478","pp. 67-72",2017,Mar.
"Shohei Handa,Shimpei Sato,Atsushi Takahashi","High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2016-111)",,"Vol. 116","No. 478","pp. 55-60",2017,Mar.
"Atsushi Takahashi","Graph is Difficult But Useful",,"Proc. the 2017 IEICE General Conference (AS-1-4)",,"Vol. A",,"pp. S6-S7",2017,Mar.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 10",,"pp. 28-38",2017,Feb.
"Shimpei Sato,Yuta Ukon,Atsushi Takahashi","Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2016-95)",,"Vol. 116","No. 415","pp. 165-170",2017,Jan.
"Ahmed Awad,Atsushi Takahashi,Chikaaki Kodama","A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model",,"IEICE Trans. Fundamentals",,"Vol. E99-A","No. 12","pp. 2363-2374",2016,Dec.
"Shimpei Sato,Hiroshi Nakatsuka,Atsushi Takahashi","Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection",,"Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016)",,,,"pp. 60-65",2016,Oct.
"Yukihide Kohira,Atsushi Takahashi,Tomomi Matsui,Chikaaki Kodama,Shigeki Nojima,Satoshi Tanaka","Manufacturability-aware Mask Assignment in Multiple Patterning Lithography",,"Proc. the 2016 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2016)",,,,"pp. 538-541",2016,Oct.
"Akinori NISHIHARA,Yuji KAGOHASHI,Atsushi TAKAHASHI,Akira YAMADA","Six University Human Assets Promotion Program for Innovative Education and Research (6U-HAPPIER)","32nd Annual Conference of JSET","32nd Annual Conference of JSET",,,"  1a-B107-01",,2016,Sept.
"Yusuke Kimura,Shimpei Sato,Atsushi Takahashi","Flexible Two-Colorable Routing for Self-Aligned Double Patterning",,"Proc. DA Symposium 2016, IPSJ Symposium Series",,"Vol. 2016","No. 6","pp. 26-31",2016,Sept.
"Shouhei Handa,Atsushi Takahashi,Kazuhide Nakata,Tomomi Matsui","Layout Decomposition Method by Positive Semidefinite Relaxationwith Pseudo Stitch Edge for TPL",,"Proc. the 29th Workshop on Circuits and Systems",,,,"pp. 214-219",2016,May
"Ahmed Awad,Atsushi Takahashi","A Lithographic Mask Manufacturability and Pattern Fidelity Aware OPC Algorithm",,"Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2016)",,,,"pp. 1-4",2016,Apr.
"Shouhei Handa,Atsushi Takahashi,Kazuhide Nakata,Tomomi Matsui","A correction term for positive semidefinite relaxation of MPL layout decomposition",,"Proc. the 2016 IEICE General Conference (A-6-12)",,"Vol. A",,"p. 86",2016,Mar.
"Toshiyuki Hongo,Atsushi Takahashi","Self-Aligned Quadruple Patterning-Aware Three-Color Grid Routing with Different Color Net","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2015-135)",,"Vol. 115","No. 465","pp. 137-142",2016,Mar.
"Ahmed Awad,Atsushi Takahashi,Chikaaki Kodama","A Fast Manufacturability Aware Optical Proximity Correction (OPC) Algorithm with Adaptive Wafer Image Estimation",,"Proc.  Design, Automation and Test in Europe (DATE 2016)",,,,"pp. 49-54",2016,Mar.
"Hiroshi Nakatsuka,Atsushi Takahashi","Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2015-140)",,"Vol. 115","No. 465","pp. 167-172",2016,Mar.
"Takeshi Ihara,Toshiyuki Hongo,Atsushi Takahashi,Chikaaki Kodama","Grid-based Self-Aligned Quadruple Patterning Aware Two Dimensional Routing Pattern",,"Proc.  Design, Automation and Test in Europe (DATE 2016)",,,,"pp. 241-244",2016,Mar.
"Yukihide Kohira,Chikaaki Kodama,Tomomi Matsui,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process",,"Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3)",,"Vol. 15","No. 2","pp. 1-7",2016,Mar.
"Pattanusorn, W.,Nilkhamhang, I.,Kittipiyakul, S.,Ekkachai, K.,Atsushi Takahashi","Passenger estimation system using Wi-Fi probe request",,"7th International Conference on Information Communication Technology for Embedded Systems 2016, IC-ICTES 2016",,,,"pp. 67-72",2016,
"Takeshi Ihara,Atsushi Takahashi","Effective Routing Pattern Generation with an Optimum Tertiary Routing Algorithm for Self-Aligned Quadruple Patterning","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2015-53)",,"Vol. 115","No. 338","pp. 93-98",2015,Dec.
"Yuta Nakatani,Atsushi Takahashi","A Length Matching Routing Algorithm for Set-Pair Routing Problem",,"IEICE Trans. Fundamentals",,"Vol. E98-A","No. 12","pp. 2565-2571",2015,Dec.
"Ahmed Awad,Atsushi Takahashi","Mask Manufacturability Aware Post OPC Algorithm For Optical Lithography",,"Proc. DA Symposium 2015, IPSJ Symposium Series",,"Vol. 2015",,"pp. 119-124",2015,Aug.
"Takeshi Ihara,Toshiyuki Hongo,Atsushi Takahashi","Effective Routing Pattern Generation Method for Self-Aligned Quadruple Patterning",,"Proc. DA Symposium 2015, IPSJ Symposium Series",,"Vol. 2015",,"pp. 125-130",2015,Aug.
"Yukihide Kohira,Chikaaki Kodama,Tomomi Matsui,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Mask Assignment with Tolerance for Misalignment in LELECUT Triple Patterning",,"Collection of Abstracts, NGL 2015",,,,"pp. 35-36",2015,July
"Takeshi Ihara,Atsushi Takahashi,Chikaaki Kodama","Effective two-dimensional pattern generation for self-aligned double patterning",,"Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2015)",,,,"pp. 2141-2144",2015,May
"Chikaaki Kodama,Hirotaka Ichikawa,Koichi Nakayama,Fumiharu Nakajima,Shigeki Nojima,Toshiya Kotani,Takeshi Ihara,Atsushi Takahashi.","Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods",,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)",,"Vol. 34","No. 5","pp. 753-765",2015,May
"Toshiyuki Hongo,Atsushi Takahashi","NP-completeness of Routing Problem with Bend Constraint","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2015-3)",,"Vol. 115","No. 21","pp. 13-18",2015,May
"Noriyuki Takahashi,Takeshi Ihara,Atsushi Takahashi","A cut-pattern reduction method for routing in Self-Aligned Double Patterning","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-154)",,"Vol. 114","No. 476","pp. 7-12",2015,Mar.
"Yuichiro Tanaka,Atsushi Takahashi","Faster Numberlink solution using possibilities of topological routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-155)",,"Vol. 114","No. 476","pp. 13-18",2015,Mar.
"Ahmed Awad,Atsushi Takahashi","A Fast Lithographic Mask Correction Algorithm","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-153)",,"Vol. 114","No. 476","pp. 1-6",2015,Mar.
"Takeshi Ihara,Atsushi Takahashi,Chikaaki Kodama","Rip-up and Reroute based Routing Algorithm for Self-Aligned Double Patterning",,"Proc. the 19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2015)",,,,"pp. 83-88",2015,Mar.
"Yukihide Kohira,Chikaaki Kodama,Tomomi Matsui,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware mask assignment using positive semidefinite relaxation in LELECUT triple patterning",,"Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270B",,,,"  1-9",2015,Mar.
"Satoshi Ohtsuki,Atsushi Takahashi","An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-181)",,"Vol. 114","No. 476","pp. 159-164",2015,Mar.
"Yuta Nakatani,Atsushi Takahashi","Zero-weighted Cycle Finding Method for Exchanging Pin Pair on Set-Pair Rouitng","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-156)",,"Vol. 114","No. 476","pp. 19-24",2015,Mar.
"Yukihide Kohira,Tomomi Matsui,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Fast Mask Assignment using Positive Semidefinite Relaxation in LELECUT Triple Patterning Lithography",,"Proc. Asia and South Pacific Design Automation Conference 2015 (ASP-DAC 2015)",,,,"pp. 665-670",2015,Jan.
"Julkananusar, A.,Nilkhamhang, I.,Vanijjirattikhan, R.,Atsushi Takahashi","Quadrotor tuning for attitude control based on PID controller using fictitious reference iterative tuning (FRIT)",,"2015 6th International Conference on Information and Communication Technology for Embedded Systems, IC-ICTES 2015",,,,,2015,
"Yukihide Kohira,Atsushi Takahashi","2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E97-A","No. 12","pp. 2459-2466",2014,Dec.
"Yiqiang Sheng,Atsushi Takahashi","A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization",,"IEICE Trans. Fundamentals",,"Vol. E97-A","No. 12","pp. 2418-2426",2014,Dec.
"Yuta Nakatani,Atsushi Takahashi","A Method for Total Length and Length Difference Reduction for Set-Pair Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-87)",,"Vol. 114","No. 328","pp. 111-116",2014,Nov.
"Atsushi Takahashi,Ahmed Awad,Yukihide Kohira,Tomomi Matsui,Chikaaki Kodama,Shigeki Nojima,Satoshi Tanaka","[Invited] Multi Patterning Techniques for Manufacturability Enhancement in Optical Lithography",,"Proc. the 2014 International Conference on Integrated Circuits, Design, and Verification (ICDV 2014)",,,,"pp. 117-122",2014,Nov.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A Fast Process Variation and Pattern Fidelity Aware Mask Optimization Algorithm",,"Proc. IEEE/ACM 2014 International Conference on Computer-Aided Design (ICCAD 2014)",,,,"pp. 238-245",2014,Nov.
"Tomomi Matsui,Yukihide Kohira,Chikaaki Kodama,Atsushi Takahashi","Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography","the 25th International Symposium on Algorithms and Computation (ISAAC 2014)","Algorithms and Computation, Lecture Notes in Computer Science",,"  LNCS 8889",,"pp. 365?375",2014,Nov.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A Process Variability Band Area Reduction Algorithm For Optical Lithography",,"Proc. the 2014 IEICE Society Conference (A-3-6)",,"Vol. A",,"p. 50",2014,Sept.
"Taisuke Sato,Atsushi Takahashi,Toshiya Itoh,Shuichi Ueno","情報基礎数学",,,"オーム社",,,,2014,Sept.
"Yuichiro Tanaka,Atsushi Takahashi","Numberlink solver based on CHORD-LAST method with area decomposition",,"Proc. DA Symposium 2014, IPSJ Symposium Series",,"Vol. 2014",,"pp. 221-226",2014,Aug.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","Mask Optimization With Minimal Number of Convolutions Using Intensity Difference Map",,"Proc. DA Symposium 2014, IPSJ Symposium Series",,"Vol. 2014",,"pp. 145-150",2014,Aug.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A New Intensity Based Edge Placement Error Optimization Algorithm for Optical Lithography",,"Proc. the 27th Workshop on Circuits and Systems",,,,"pp. 422-427",2014,Aug.
"Yukihide Kohira,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Fast Mask Assignment Method Considering Yield for LELE Double Patterning",,"Collection of Abstracts, NGL 2014",,,,"pp. 41-42",2014,July
"Yukihide Kohira,Tomomi Matsui,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-6)",,"Vol. 114","No. 59","pp. 27-32",2014,May
"Yusaku Yamamoto,Atsushi Takahashi","An Enhancement of Length Difference Reduction Algorithm for Set Pair Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2013-142)",,"Vol. 113","No. 454","pp. 49-54",2014,Mar.
"Yukihide Kohira,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware decomposition for LELE double patterning",,"Proc. SPIE   9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530T",,,,"  1-10",2014,Mar.
"Yoko Yokoyama,Keishi Sakanushi,Yukihide Kohira,Atsushi Takahashi,Chikaaki Kodama,Satoshi Tanaka,Shigeki Nojima","Localization concept of re-decomposition area to fix hotspots for LELE process",,"Proc. SPIE   9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530V",,,,"  1-8",2014,Mar.
"Takeshi Ihara,Atsushi Takahashi,Chikaaki Kodama","Self-Aligned Double Patterning-Aware Modified Two-color Grid Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2013-150)",,"Vol. 113","No. 454","pp. 93-98",2014,Mar.
"Miyabe Yutaro,Atsushi Takahashi,Tomomi Matsui,Yukihide Kohira,Yoko Yokoyama","Local Pattern Modification Method for Lithographical ECO in Double Patterning","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2013-149)",,"Vol. 113","No. 454","pp. 87-92",2014,Mar.
"Yukihide Kohira,Atsushi Takahashi","2-SAT based Linear Time Optimum Two-Domain Clock Skew Scheduling",,"Proc. Asia and South Pacific Design Automation Conference 2014 (ASP-DAC 2014)",,,,"pp. 173-178",2014,Jan.
"Yiqiang Sheng,Atsushi Takahashi","A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 6",,"pp. 94-100",2013,Aug.
"Satosi Otsuki,Atsushi Takahashi","The Evaluation of Performance of Multiplier with Variable-Latency Technology on FPGA",,"Proc. DA Symposium 2013, IPSJ Symposium Series",,"Vol. 2013","No. 3","pp. 157-162",2013,Aug.
"Yukihide Kohira,Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Overlap Area Maximization in Stitch Selection for LELE Double Patterning",,"Proc. the 26th Workshop on Circuits and Systems",,,,"pp. 466-471",2013,July
"Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Yukihide Kohira,Satoshi Tanaka,Keishi Sakanushi,Jiro Higuchi,Shigeki Nojima","A Study of Robust Stitch Design for Litho-etch-litho-etch Double Patterning","Design for Manufacturability and Yield 2013 (DFM&Y2013)",,,,,,2013,June
"Yukihide Kohira,Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Minimum Cost Stitch Selection in LELE Double Patterning","Design for Manufacturability and Yield 2013 (DFM&Y2013)",,,,,,2013,June
"Kyosuke Shinoda,Atsushi Takahashi","A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2012-149)",,"Vol. 112","No. 451","pp. 77-82",2013,Mar.
"Kenta Ando,Atsushi Takahashi","Fast Performance Estimation Method for Variable Latency Circuits with Error Detection/Correction Mechanism","System LSI Design Methodology","IPSJ SIG Technical Reports",,"Vol. 2013-SLDM-160","No. 16","pp. 1-6",2013,Mar.
"Atsushi Takahashi","Dawn of Computer-aided Design - from Graph-theory to Place and Route -",,"Proc. ACM International Symposium on Physical Design  (ISPD 2013)",,,,"p. 58",2013,Mar.
"Kyosuke Shinoda,Atsushi Takahashi","A Study of Effects of Length Control in Trunk Routing Problem",,"Proc. the 2013 IEICE General Conference (A-3-6)",,"Vol. A",,"p. 66",2013,Mar.
"Chikaaki Kodama,Hirotaka Ichikawa,Koichi Nakayama,Toshiya Kotani,Shigeki Nojima,Shoji Mimotogi,Shinji Miyamoto,Atsushi Takahashi","Self-Aligned Double and Quadruple Patterning Aware Grid Routing with Hotspots Control",,"Proc. Asia and South Pacific Design Automation Conference 2013 (ASP-DAC 2013)",,,,"pp. 267-272",2013,Jan.
"Dai Akita,Kenta Ando,Atsushi Takahashi","Fast Estimation of Dynamic Delay Distribution","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2012-55)",,"Vol. 112","No. 245","pp. 83-88",2012,Oct.
"Yiqiang Sheng,Atsushi Takahashi","A Simulated Annealing Based Approach to Integrated Circuit Layout Design",,"Simulated Annealing - Single and Multiple Objective Problems","InTech",,,"pp. 239-260",2012,Oct.
"Yukihide Kohira,Atsushi Takahashi","An Optimum 2-Clustering Method in General-Synchronous Framework",,"Proc. the 25th Workshop on Circuits and Systems",,,,"pp. 178-183",2012,July
"Atsushi Takahashi","Delay-variation Aware Adaptive Circuits - High-performance Circuits under Delay Variation Environments -",,"Proc. the 25th Workshop on Circuits and Systems",,,,"pp. 184-189",2012,July
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization",,"Proc. the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012)",,,,"pp. 227-232",2012,Mar.
"Kenta Ando,Atsushi Takahashi","Performance Evaluation of Various Configuration of Adder in Variable Latency Circuits with Error Detection/Correction Mechanism",,"Proc. the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012)",,,,"pp. 549-554",2012,Mar.
"Yuta Ukon,Kenta Ando,Atsushi Takahashi","Performance of the Evaluation of a Variable-Latency-Circuit on FPGA","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-141)",,"Vol. 111","No. 450","pp. 127-132",2012,Mar.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","An Equi-Length Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing",,"Proc. the 2012 IEICE General Conference (A-3-3)",,"Vol. A",,"p. 87",2012,Mar.
"Yukihide Kohira,Atsushi Takahashi","An Any-Angle Routing Method using Quasi-Newton Method",,"Proc. Asia and South Pacific Design Automation Conference 2012 (ASP-DAC 2012)",,,,"pp. 145-150",2012,Jan.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","Single-Layer Trunk Routing Using Minimal 45-Degree Lines",,"IEICE Trans. Fundamentals",,"Vol. E94-A","No. 12","pp. 2510-2518",2011,Dec.
"Atsushi Takahashi","Foreword",,"IEICE Trans. Fundamentals",,"Vol. E94-A","No. 12","p. 2481",2011,Dec.
"Atsushi Takahashi","Adaptive Computing Oriented Circuit Synthesis",,"Proc. Ambient GCOE International Workshop on System LSI : Ambient SoC - Now and Beyond",,,,"p. 6",2011,Nov.
"Yusaku Yamamoto,Atsushi Takahashi","A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-87)",,"Vol. 111","No. 324","pp. 203-208",2011,Nov.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-88)",,"Vol. 111","No. 324","pp. 209-214",2011,Nov.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","RRA-Based Multi-Objective Optimization to Mitigate the Worst Cases of Placement",,"Proc. IEEE 9th International Conference on ASIC (ASICON 2011)",,,,"pp. 357-360",2011,Oct.
"Atsushi Takahashi","On set pair routing problem","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-44)",,"Vol. 111","No. 216","pp. 23-28",2011,Sept.
"Yukihide Kohira,Atsushi Takahashi","An Iterative Improvement Method for Any-Angle Routing using Quasi-Newton Method",,"Proc. the 2011 IEICE Society Conference (A-3-20)",,"Vol. A",,"p. 94",2011,Sept.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-42)",,"Vol. 111","No. 216","pp. 11-16",2011,Sept.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","A Stochastic Optimization Method to Solve General Placement Problem Effectively",,"Proc. DA Symposium 2011, IPSJ Symposium Series",,"Vol. 2011","No. 5","pp. 27-32",2011,Aug.
"Yukihide Kohira,Atsushi Takahashi","An Any-Angle Routing Method using Quasi-Newton Method",,"Proc. the 24th Workshop on Circuits and Systems",,,,"pp. 425-430",2011,Aug.
"Kenta Ando,Atsushi Takahashi","Performance Evaluation of Various Configurations of Adder in Error Detection/Correction Circuits","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-33)",,"Vol. 111","No. 103","pp. 147-152",2011,July
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement",,"Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011)",,,,"pp. 96-101",2011,July
"Masafumi Inoue,Yuuta Ukon,Atsushi Takahashi","An evaluation of error detection/correction circuits by gate level simulation","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2010-141)",,"Vol. 110","No. 432","pp. 147-152",2011,Mar.
"Yuki Kouno,Yasuhiro Takashima,Atsushi Takahashi","CRP : Efficient Topology Modification for Minimum Perturbation Placement Realization","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2010-138)",,"Vol. 110","No. 432","pp. 129-134",2011,Mar.
"Yuuta Ukon,Masafumi Inoue,Atsushi Takahashi,Kenji Taniguchi","Behavior Verification of a Variable Latency Circuit on FPGA","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2010-142)",,"Vol. 110","No. 432","pp. 153-158",2011,Mar.
"Yukihide Kohira,Atsushi Takahashi","CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles",,"IEICE Trans. Fundamentals",,"Vol. E93-A","No. 12","pp. 2380-2388",2010,Dec.
"Atsushi Takahashi","[Invited Talk] An overview of VLSI design automation and its future prospective",,"The Japan Society of Applied Physics, Silicon Technology Division",,,"No. 128","pp. 42-43",2010,Nov.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","Single-Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing",,"Proc. the 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010)",,,,"pp. 278-283",2010,Oct.
"Yuki Kouno,Yasuhiro Takashima,Atsushi Takahashi","Fast Optimization on Minimum Perturbation Placement Realization","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2010-51)",,"Vol. 110","No. 210","pp. 55-60",2010,Sept.
"Yukihide Kohira,Atsushi Takahashi","[Invited Talk] Length Matching Routing on Single Layer for PCB Routing Design","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2010-47)",,"Vol. 110","No. 210","pp. 31-36",2010,Sept.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","A Congested Area Specification for Single Layer Printed Circuit Board Routing",,"Proc. the 2010 IEICE Society Conference (A-3-4)",,"Vol. A",,"p. 66",2010,Sept.
"Yukihide Kohira,Atsushi Takahashi","An Evaluation of Clock Tree Based on Clustering in General-Synchronous Framework",,"Proc. the 2010 IEICE Society Conference (A-3-1)",,"Vol. A",,"p. 63",2010,Sept.
"Masafumi Inoue,Yuuta Ukon,Atsushi Takahashi,Kenji Taniguchi","Evaluation of Circuit Architecture and Performance of Error-Detection-Correction Mechanism",,"Proc. DA Symposium 2010, IPSJ Symposium Series",,"Vol. 2010","No. 7","pp. 123-128",2010,Sept.
"Atsushi Takahashi","Approaches for Improving Synchronous Circuit Performance","Physical Design Issues for Highly Integrated LSI and SiP, IEEE Circuits and Systems Society Kansai Chapter",,,,,,2010,July
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","An Efficient Congested Area Specification And Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Rouitng","Committee on VLSI Design Technologies","IEICE Technical Report (VLD2010-9)",,"Vol. 110","No. 36","pp. 79-84",2010,May
"Masaki Kinoshita,Yoichi Tomioka,Atsushi Takahashi","Evaluation of a Detail Via Arrangement Method for 2-Layer Ball Grid Array Packages","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-117)",,"Vol. 109","No. 462","pp. 109-114",2010,Mar.
"Nobuyoshi Takahashi,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-115)",,"Vol. 109","No. 462","pp. 97-102",2010,Mar.
"Yuuta Ukon,Masafumi Inoue,Atsushi Takahashi,Kenji Taniguchi","Performance evaluation of ADDER with Error-Detection-Correction Mechanism","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-121)",,"Vol. 109","No. 462","pp. 133-138",2010,Mar.
"Yukihide Kohira,Atsushi Takahashi","Clustering Method for Low Power Clock Tree in General Syncrhonous Framework","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-119)",,"Vol. 109","No. 462","pp. 121-126",2010,Mar.
"Nobuyoshi Takahashi,Atsushi Takahashi","Fast Estimation of Peak Power by Appropriate Input Vector Selection","Student Forum at Asia and South Pacific Design Automation Conference 2010(ASP-DAC 2010)",,,,,,2010,Jan.
"Yukihide Kohira,Atsushi Takahashi","CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles",,"Proc. Asia and South Pacific Design Automation Conference 2010 (ASP-DAC 2010)",,,,"pp. 281-286",2010,Jan.
"Nobuyoshi Takahashi,Atsushi Takahashi","Fast Estimation of Peak Power by Appropriate Input Vector Selection","The 6th IEEE Tokyo Young Researchers Workshop",,,,,,2009,Dec.
"Yuuta Ukon,Atsushi Takahashi,Kenji Taniguchi","[Poster Presentation] An evaluation of delay error rate of an adder in terms of clock period","Technical Committee on Integrated Circuits and Devices","IEICE Technical Report (ICD2009-91)",,"Vol. 109","No. 336","pp. 77-81",2009,Dec.
"Yukihide Kohira,Suguru Suehiro,Atsushi Takahashi","A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 12","pp. 2971-2978",2009,Dec.
"Yoichi Tomioka,Yoshiaki Kurata,Yukihide Kohira,Atsushi Takahashi","MILP-based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 12","pp. 2998-3006",2009,Dec.
"Atsushi Takahashi","New Design Methodologies for Synchronous Circuits",,"Special Papers of IEEJ the 2009 International Analog VLSI Workshop",,,,"pp. I2-1-I2-4",2009,Nov.
"Yukihide Kohira,Atsushi Takahashi","A River Routing Method for Single Layer with Obstacles by Area Partition",,"Proc. the 2009 IEICE Society Conference (A-3-9)",,"Vol. A",,"p. 58",2009,Sept.
"Atsushi Takahashi","Recent Advances in Routing Control Technology",,"Proc. Japan-Taiwan Semiconductor Electronic Design Automation (EDA) Science and Technology Symposium",,,,"pp. 143-150",2009,Sept.
"Yukihide Kohira,Atsushi Takahashi","A Wall Generation for Trunk Routing of Multiple Nets on Single Layer","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-31)",,"Vol. 109","No. 201","pp. 13-18",2009,Sept.
"Masaki Kinoshita,Yoichi Tomioka,Atsushi Takahashi","A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-30)",,"Vol. 109","No. 201","pp. 7-12",2009,Sept.
"Yoichi Tomioka,Atsushi Takahashi","Top Layer Plating Lead Maximization for BGA Packages",,"Proc. the 2009 IEICE Society Conference (A-3-10)",,"Vol. A",,"p. 59",2009,Sept.
"Nobuyoshi Takahashi,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","Fast Estimation of Peak Power by Appropriate Input Vector Selection",,"Proc. DA Symposium 2009, IPSJ Symposium Series",,"Vol. 2009","No. 7","pp. 13-18",2009,Aug.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","Octilinear Routing Method with Congestion Relaxation by Slant Lines","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-23,CAS2009-18,SIP2009-35)",,"Vol. 109","No. 111","pp. 97-102",2009,July
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 6","pp. 1433-1441",2009,June
"Masafumi Inoue,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","A RST Construction Method for Vertices with Maximum Path Length","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2009-4)",,"Vol. 109","No. 34","pp. 31-36",2009,May
"Yukihide Kohira,Shuhei Tani,Atsushi Takahashi","Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 4","pp. 1106-1114",2009,Apr.
"Suguru Suehiro,Yukihide Kohira,Atsushi Takahashi","A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2008-137)",,"Vol. 108","No. 487","pp. 59-64",2009,Mar.
"Yoshiaki Kurata,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages",,"Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)",,,,"pp. 307-312",2009,Mar.
"Shun Gokita,Yukihide Kohira,Atsushi Takahashi","A Fast Approximation Method of Maximum Operation in Statistical Static Timing Analysis for Achieving Specified Yield",,"Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)",,,,"pp. 364-369",2009,Mar.
"Yuki Kouno,Yasuhiro Takashima,Atsushi Takahashi","Fast Optimization on Minimum Perturbation Placement Realization","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2008-138)",,"Vol. 108","No. 487","pp. 65-70",2009,Mar.
"Hiroyoshi Hashimoto,Yukihide Kohira,Atsushi Takahashi","A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2008-134)",,"Vol. 108","No. 487","pp. 47-52",2009,Mar.
"Shuhei Tani,Yukihide Kohira,Atsushi Takahashi","A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2008-135)",,"Vol. 108","No. 487","pp. 53-58",2009,Mar.
"Yukihide Kohira,Suguru Suehiro,Atsushi Takahashi","A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound",,"Proc. Asia and South Pacific Design Automation Conference 2009 (ASP-DAC 2009)",,,,"pp. 600-605",2009,Jan.
"Yukihide Kohira,Shuhei Tani,Atsushi Takahashi","Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework",,"Proc. the 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2008)",,,,"pp. 1680-1683",2008,Dec.
"Yosuke Takahashi,Yukihide Kohira,Atsushi Takahashi","A Fast Clock Scheduling for Peak Power Reduction in LSI",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 12","pp. 3803-3811",2008,Dec.
"Yoichi Tomioka,Atsushi Takahashi","A Semi-Monotonic Routing Method for Fanin Type Ball Grid Array Packages",,"Proc. the 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2008)",,,,"pp. 1550-1553",2008,Dec.
"Masato Inagi,Yasuhiro Takashima,Yuichi Nakamura,Atsushi Takahashi","Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 12","pp. 3539-3547",2008,Dec.
"Yukihide Kohira,Atsushi Takahashi","CAFE router: A Fast Connectivity Aware Multi-net Routing Algorithm for Routing Grid with Obstacles","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2008-72,DC2008-40)",,"Vol. 108","No. 298","pp. 73-78",2008,Nov.
"Yukihide Kohira,Atsushi Takahashi","A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 10","pp. 3030-3037",2008,Oct.
"Yoshiaki Kurata,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2008-55)",,"Vol. 108","No. 224","pp. 49-54",2008,Sept.
"Shun Gokita,Yukihide Kohira,Atsushi Takahashi","A Computation Method of Maximum of Achieving Specified Yield for Statistical Static Timing Analysis",,"Proc. DA Symposium 2008, IPSJ Symposium Series",,"Vol. 2008","No. 7","pp. 193-198",2008,Aug.
"Masato Inagi,Yasuhiro Takashima,Yuichi Nakamura,Atsushi Takahashi","ILP-Based Optimization of Time-Multiplexed I/O Assignment for Multi-FPGA Systems",,"Proc. the 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008)",,,,"pp. 1800-1803",2008,May
"Yukihide Kohira,Suguru Suehiro,Atsushi Takahashi","A Maximum Wire Length Router in Routing Area with Obstacles using Upper Bound Estimation Considering Connectivity",,"Proc. the 21st Workshop on Circuits and Systems in Karuizawa",,,,"pp. 569-574",2008,Apr.
"Yukihide Kohira,Shiyuuhei Tani,Atsushi Takahashi","Clock Scheduling Method and Delay Insertion Method for Minimization of Inserted Delay",,"Proc. the 21st Workshop on Circuits and Systems in Karuizawa",,,,"pp. 629-634",2008,Apr.
"Naoki Sato,Yoichi Tomioka,Atsushi Takahashi","Global Routing Method of Plating Lead for 2-Layer BGA Packages","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2007-154)",,"Vol. 107","No. 507","pp. 61-66",2008,Mar.
"Tsutomu Ishida,Yukihide Kohira,Atsushi Takahashi","A Fast Modification Algorithm for Shortest Path Tree and its Performance Evaluation","Technical Committee on Circuits and Systems","IEICE Technical Report (CAS2007-98)",,"Vol. 107","No. 476","pp. 25-30",2008,Feb.
"Suguru Suehiro,Yukihide Kohira,Atsushi Takahashi","A note of an estimation of the maximum wire length in the area with obstacle","Technical Committee on Circuits and Systems","IEICE Technical Report (CAS2007-97)",,"Vol. 107","No. 476","pp. 19-23",2008,Feb.
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Modification Method of Monotonic Via Assignment for 2-layer Ball Grid Array Packages",,"Proc. Asia and South Pacific Design Automation Conference 2008 (ASP-DAC 2008)",,,,"pp. 238-243",2008,Jan.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements",,"IEICE Trans. Fundamentals",,"Vol. E90-A","No. 12","pp. 2736-2742",2007,Dec.
"TAISUKE SATO,Atsushi Takahashi,Toshiya Itoh,Shuichi UENO","情報基礎数学",,,"昭晃堂",,,,2007,Oct.
"Yoichi Tomioka,Atsushi Takahashi","Fast Monotonic Via Assignment Excluding Mold Gates for 2-Layer Ball Grid Array Packages",,"Proc. the 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2007)",,,,"pp. 192-197",2007,Oct.
"Yukihide Kohira,Atsushi Takahashi","Evaluation of Register Relocation Method for General Synchronous Framework",,"Proc. DA Symposium 2007, IPSJ Symposium Series",,"Vol. 2007","No. 7","pp. 193-198",2007,Aug.
"Yoichi Tomioka,Atsushi Takahashi","A Semi-Monotonic Via Assignment Method for 2-layer Ball Grid Array Packages",,"Proc. DA Symposium 2007, IPSJ Symposium Series",,"Vol. 2007","No. 7","pp. 145-150",2007,Aug.
"Hiroyoshi Hashimoto,Yukihide Kohira,Atsushi Takahashi","An Improved Clock Tree Synthesis Method by Using CAD Tools for General Synchronous Circuits",,"Proc. DA Symposium 2007, IPSJ Symposium Series",,"Vol. 2007","No. 7","pp. 199-204",2007,Aug.
"Yukihide Kohira,Atsushi Takahashi","A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework",,"Proc. the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)",,,,"pp. 1795-1798",2007,May
"Hiroki Furuya,Yukihide Kohira,Atsushi Takahashi","A fast maximum delay estimation method for specified yield by statistical static timing analysis","System LSI Design Methodology","IPSJ SIG Technical Reports (2007-SLDM-130)",,"Vol. 2007","No. 39","pp. 75-79",2007,May
"Yukihide Kohira,Atsushi Takahashi","Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization",,"IEICE Trans. Fundamentals",,"Vol. E90-A","No. 4","pp. 800-807",2007,Apr.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Delay Balancing by Min-Cut Algorithm for Reducing the Area of Pipelined Circuits",,"Proc. the 20th Workshop on Circuits and Systems in Karuizawa",,,,"pp. 643-648",2007,Apr.
"Yosuke Takahashi,Yukihide Kohira,Atsushi Takahashi","A Fast Clock Scheduling for Peak Power Reduction in LSI",,"Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI 2007)",,,,"pp. 582-587",2007,Mar.
"Yosuke Harada,Hiroyoshi Hashimoto,Yukihide Kohira,Atsushi Takahashi","A Clock Tree Synthesis Method by Using CAD Tools for General-synchronous Circuits","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-127)",,"Vol. 106","No. 548","pp. 49-53",2007,Mar.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits",,"Proc. the 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006)",,,,"pp. 802-805",2006,Dec.
"Yoichi Tomioka,Atsushi Takahashi","Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E89-A","No. 12","pp. 3551-3559",2006,Dec.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Multi-clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits",,"IEICE Trans. Fundamentals",,"Vol. E89-A","No. 12","pp. 3435-3442",2006,Dec.
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-76)",,"Vol. 106","No. 389","pp. 25-30",2006,Nov.
"Yukihide Kohira,Atsushi Takahashi","A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-70)",,"Vol. 106","No. 388","pp. 33-38",2006,Nov.
"Yosuke Takahashi,Atsushi Takahashi","Power Wave Smoothing by Clock Scheduling for Peak Power Reduction in LSI","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-69)",,"Vol. 106","No. 388","pp. 27-32",2006,Nov.
"Atsushi Takahashi","[Invited Talk] General synchronous circuits using global clock - design methodologies, tools, and prospects -","System LSI Design Methodology","IPSJ SIG Technical Reports (2006-SLDM-126)",,"Vol. 2006","No. 111","pp. 159-164",2006,Oct.
"Yosuke Takahashi,Atsushi Takahashi","Peak Power Reduction in LSI by Clock Scheduling","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-35)",,"Vol. 106","No. 254","pp. 7-12",2006,Sept.
"Yoichi Tomioka,Atsushi Takahashi","Monotonic Parallel Routing to Reduce Maximum Congestion for Ball Grid Array Packages",,"Proc. DA Symposium 2006, IPSJ Symposium Series",,"Vol. 2006","No. 7","pp. 19-24",2006,July
"Tsutomu Ishida,Yukihide Kohira,Atsushi Takahashi","Performance Evaluation of Negative Cycle Detection Algorithms","Algorithms","IPSJ SIG Technical Reports (2006-AL-107)",,"Vol. 2006","No. 71","pp. 45-50",2006,July
"Atsushi Takahashi","同期式回路の革新的設計方法論の確立",,"東工大クロニクル",,,"No. 411","pp. 6-8",2006,June
"Yukihide Kohira,Chikaaki Kodama,Kunihiro Fujiyoshi,Atsushi Takahashi","Evaluation of 3D-Packing Representations for Scheduling of Dynamically Reconfigurable Systems",,"Proc. the 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)",,,,"pp. 4487-4490",2006,May
"Yukihide Kohira,Atsushi Takahashi","Clock Period Minimization Method of Semi-Synchronous Circuits by Register Relocation",,"Proc. the 19th Workshop on Circuits and Systems in Karuizawa",,,,"pp. 259-264",2006,Apr.