"T. Akushichi,Y. Takamura,Y. Shiotsu,S. Yamamoto,S. Sugahara","Spin Injection Behavior of CoFe/MgO/Si Tunnel Contacts: Effects of Radical Oxygen Annealing",,"J. Electron. Mater.",,"vol. 52",,"pp. 6902-6910",2023,Aug.
"Osamu Yamazaki,Yusaku Shiotsu,SATOSHI SUGAHARA,Shuichiro Yamamoto","FinFETを用いた低電圧駆動不揮発性SRAM (NV-SRAM)の設計",,,,,,,2022,Sept.
"Taketo Kato,Yusaku Shiotsu,SATOSHI SUGAHARA,Shuichiro Yamamoto","ニアスレッショルド電圧駆動ULVR-SRAMのパワーゲーティング性能","第83回応用物理学会秋季学術講演会",,,,,,2022,Sept.
"Katsutoshi Ito,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","新型超低電圧リテンションSRAM (ULVR-SRAM)セルの提案","第83回応用物理学会秋季学術講演会",,,,,,2022,Sept.
"Hiroki Yano,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","超低電圧リテンションSRAMのパワーゲーティング性能とアーキテクチャ","第69回応用物理学会春季学術講演会",,,,,,2022,Mar.
"Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","不揮発性SRAM：エッジコンピューティングの革新的低消費電力技術",,,,,,,2021,Oct.
"Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","ULVR-SRAMを用いたBNNアクセラレータの提案と性能予測","第82回応用物理学会秋季学術講演会",,,,,,2021,Sept.
"Shuhei Saito,Yusaku Shiotsu,Takumi Hara,Shuichiro Yamamoto,SATOSHI SUGAHARA","ボディバイアス制御ULVR-SRAMの設計と解析","第82回応用物理学会秋季学術講演会",,,,,,2021,Sept.
"Takumi Hara,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","ニアスレッショルド電圧動作ULVR-SRAMマクロの設計と解析","第82回応用物理学会秋季学術講演会",,,,,,2021,Sept.
"Tsubasa Matsuzaki,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","バルクデバイスを用いた超低電圧リテンションFlip-Flopの設計と解析","第82回応用物理学会秋季学術講演会",,,,,,2021,Sept.
"Hayato Yoshida,Yusaku Shiotsu,Daiki Kitagata,Shuichiro Yamamoto,Satoshi Sugahara","Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches",,"IEEE Open Journal of Circuits and Systems",,"Vol. 2",,"pp. 520-533",2021,Aug.
"Yusaku Shiotsu,Hayato Yoshida,Shuichiro Yamamoto,SATOSHI SUGAHARA","ボディバイアス効果を用いたULVR-SRAMセルの設計とそのパワーゲーティング性能","LSIとシステムのワークショップ2021",,,,,,2021,May
"Takumi Hara,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","ニアスレッショルド電圧動作超低電圧リテンションSRAMの設計と性能解析","LSIとシステムのワークショップ2021",,,,,,2021,May
"Takumi Hara,Hayato Yoshida,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","ニアスレッショルド電圧動作ULVR-SRAMセルの設計","第68回応用物理学会春季学術講演会",,,,,,2021,Mar.
"Kenichiro Takiguchi,Yusaku Shiotsu,Tsubasa Matsuzaki,Shuichiro Yamamoto,SATOSHI SUGAHARA","超低電圧リテンションフリップフロップ（ULVR-FF）のエネルギー極小点動作","第68回応用物理学会春季学術講演会",,,,,,2021,Mar.
"Hayato Yoshida,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","ULVR-SRAMを用いたキャッシュのパワーゲーティング性能","第68回応用物理学会春季学術講演会",,,,,,2021,Mar.
"Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","超低電圧リテンションSRAM (ULVR-SRAM)のエネルギー極小点動作","第68回応用物理学会春季学術講演会",,,,,,2021,Mar.
"Hayato Yoshida,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","各種リテンションSRAMのパワーゲーティングにおける電力削減効率に関する電源遮断可能時間分布の影響","第81回応用物理学会秋季学術講演会",,,,,,2020,Sept.
"Daiki Kitagata,Hayato Yoshida,Yusaku Shiotsu,Shuichiro Yamamoto,SATOSHI SUGAHARA","新型超低電圧リテンションSRAMセルの設計と解析","第81回応用物理学会秋季学術講演会",,,,,,2020,Sept.
"Kenichiro Takiguchi,Daiki Kitagata,Tsubasa Matsuzaki,Shuichiro Yamamoto,SATOSHI SUGAHARA","新型超低電圧リテンションFFの提案","第81回応用物理学会秋季学術講演会",,,,,,2020,Sept.
"Yusaku Shiotsu,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","新型超低電圧リテンションSRAMマクロの設計と解析","第81回応用物理学会秋季学術講演会",,,,,,2020,Sept.
"Y. Shiotsu,S. Yamamoto,Y. Shuto,H. Funakubo,M. K. Kurosawa,S. Sugahara","Modeling and Design of a New Piezoelectronic Transistor for Ultralow-Voltage High-Speed Integrated Circuits",,"IEEE Trans. on Electron Devices",,"vol. 67","no. 9","pp. 3852-3860",2020,Aug.
"Hayato Yoshida,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","新型擬似不揮発性SRAMセルの提案",,,,,,,2020,Mar.
"Takumi Hara,Hayato Yoshida,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","ニアスレッショルド電圧動作擬似不揮発SRAMセルの設計と解析",,,,,,,2020,Mar.
"Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions",,,,,,,2020,Feb.
"D. Kitagata,S. Yamamoto,S. Sugahara","A New Store Energy and Latency Reduction Architecture for Nonvolatile SRAM Using STT-MTJs: Proactive Useless Data Flush Architecture","IEEE International Electron Devices Meeting (IEDM) 2019 MRAM special session",,,,,,2019,Dec.
"Kenichiro Takiguchi,Daiki Kitagata,Tsubasa Matsuzaki,Shuichiro Yamamoto,SATOSHI SUGAHARA","不揮発/擬似不揮発性FFを用いたパワーゲーティングの性能評価",,,,,,,2019,Sept.
"Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","NV-SRAMを用いたUseless dataの積極的破棄による不揮発性パワーゲーティング","第80回応用物理学会秋季学術講演会",,,,,,2019,Sept.
"Yusaku Shiotsu,Shuichiro Yamamoto,HIROSHI FUNAKUBO,Minoru Kuribayashi Kurosawa,SATOSHI SUGAHARA","新構造ピエゾエレクトロニックトランジスタを用いたFFの設計と性能","第80回応用物理学会秋季学術講演会",,,,,,2019,Sept.
"Hayato Yoshida,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","不揮発/擬似不揮発記憶を用いたSRAMのパワーゲーティング性能","第80回応用物理学会秋季学術講演会",,,,,,2019,Sept.
"Takumi Hara,Hayato Yoshida,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","各種リテンション技術を用いたSRAMのパワーゲーティング性能","第80回応用物理学会秋季学術講演会",,,,,,2019,Sept.
"Yusaku Shiotsu,Shuichiro Yamamoto,HIROSHI FUNAKUBO,Minoru Kuribayashi Kurosawa,SATOSHI SUGAHARA","Design of New Piezoelectronic Transistors and Their Ultralow-Voltage SRAM Application","IEEE 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon",,,,,,2019,Apr.
"D. Kitagata,S. Yamamoto,S. Sugahara","Design and energy-efficient architectures for nonvolatile static random access memory using magnetic tunnel junctions",,"Jpn. J. Appl. Phys",,"Vol. 58","No. SB","pp. 1-10",2019,Mar.
"Daiki Kitagata,Tsubasa Matsuzaki,Shuichiro Yamamoto,SATOSHI SUGAHARA","擬似不揮発性FFの速度性能優先設計とその回路性能","第66回応用物理学会春季学術講演会",,,,,,2019,Mar.
"Yusaku Shiotsu,Shuichiro Yamamoto,HIROSHI FUNAKUBO,Minoru Kuribayashi Kurosawa,SATOSHI SUGAHARA","新構造ピエゾエレクトロニックトランジスタの低リーク設計とそのSRAMへの応用","第66回応用物理学会春季学術講演会",,,,,,2019,Mar.
"Daiki Kitagata,Tsubasa Matsuzaki,Shuichiro Yamamoto,SATOSHI SUGAHARA","擬似不揮発性FFの速度性能優先設計とその回路性能","第66回応用物理学会春季学術講演会",,,,,,2019,Mar.
"Hayato Yoshida,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","デュアルパワースイッチを用いた擬似不揮発性SRAMの設計と解析","第66回応用物理学会春季学術講演会",,,,,,2019,Mar.
"D. Kitagata,S. Yamamoto,S. Sugahara","Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters","2nd New Generation of Circuits & Systems Conference (NGCAS2018)",,,,,"pp. 182-185",2018,Nov.
"Kitagata,H. Yoshida,S. Yamamoto,S. Sugahara","Virtually Nonvolatile Retention SRAM cell Using Dual-Mode Inverters","2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S Conference 2018)",,,,,,2018,Oct.
"D. Kitagata,S. Yamamoto,S. Sugahara","A New Architecture of Store Energy and Latency Reduction for Nonvolatile SRAM Based on Spintronics/CMOS-Hybrid Technology","2018 International Conference on Solid State Device and Materials (SSDM2018)",,,,,,2018,Sept.
"Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","デュアルモードインバータを用いた疑似不揮発性FFの設計と解析","第79回応用物理学会秋季学術講演会",,,,,,2018,Sept.
"Hayato Yoshida,Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","デュアルモードインバータを用いた疑似不揮発性SRAMの設計と解析","第79回応用物理学会秋季学術講演会",,,,,,2018,Sept.
"Yusaku Shiotsu,Shuichiro Yamamoto,HIROSHI FUNAKUBO,Minoru Kuribayashi Kurosawa,SATOSHI SUGAHARA","Design methodology of a new piezoelectronic transistor","The 79th JSAP Autumn Meeting",,,,," 21a-CE-8",2018,Sept.
"D. Kitagata,S. Yamamoto,S. Sugahara","Virtually Nonovolatile Retention Flip-Flop Using FinFET Technology","2018 IEEE Silicon Nanoelectronics Workshop (SNW 2018)",,,,,,2018,June
"Y. Shiotsu,S. Yamamoto,Y. Shuto,H. Funakubo,M. K. Kurosawa,S. Sugahara","Design and circuit performance of a new piezoelectronic transistor","2018 IEEE Silicon Nanoelectronics Workshop (SNW 2018)",,,,," P2-5",2018,June
"Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","階層型ストアフリー電源遮断を用いた不揮発性SRAMのエネルギー性能","第65回応用物理学会春季学術講演会",,,,,,2018,Mar.
"Y. Takamura,S. Yamamoto,H. Funakubo,M.K. Kurosawa,S. Nakagawa,S. Sugahara","Piezoelectronic magnetoresistive-device and its low-voltage MRAM application","The 65th JSAP Spring Meeting",,,,," 18p-G203-8",2018,Mar.
"Yusaku Shiotsu,Shuichiro Yamamoto,Yusuke Shuto,Hiroshi Funakubo,Minoru Kuribayashi Kurosawa,Satoshi Sugahara","Design of a new piezoelectronic transistor and its device and circuit performances","The 65th JSAP Spring Meeting",,,,," 18p-G203-7",2018,Mar.
"D. Kitagata,S. Yamamoto,S. Sugahara","Hierarchical Store-Free Architecture for Nonvolatile SRAM Using STT-MTJs","IEEE International Electron Devices Meeting (IEDM) MRAM special session 2017",,,,,,2017,Dec.
"Sugahara,Y. Shuto,S. Yamamoto,H. Funakubo,M. K. Kurosawa","Piezoelectronic Transistor for Low-Voltage High-Speed Integrated Electronics","2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S Conference 2017)",,,,,,2017,Oct.
"Daiki Kitagata,Yusuke Shuto,Shuichiro Yamamoto,SATOSHI SUGAHARA","Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating","Integrated Circuits and Devices","IEICE technical report",,"Vol. 117","No. 9","pp. 51-56",2017,Apr.
"Daiki Kitagata,Shuichiro Yamamoto,SATOSHI SUGAHARA","強磁性トンネル接合を用いた不揮発性SRAMの待機時電力削減能力","第78回応用物理学会秋季学術講演会",,,,,,2017,Mar.
"Daiki Kitagata,Yusuke Shuto,Shuichiro Yamamoto,SATOSHI SUGAHARA","不揮発性SRAMの設計とエネルギー性能の解析","第64回応用物理学会春季学術講演会",,," 16a-412-7",,,2017,Mar.
"D. Kitagata,Y. Shuto,S. Yamamoto,S. Sugahara","Analysis of Break-Even Time for Nonvolatile SRAM with SOTB Technology","Electron Device Technology and Manufacturing Conference",,," 4B-5",,,2017,Feb.
"Y. Takamura,Y. Shuto,S. Yamamoto,H. Funakubo,M. Kurosawa,S. Nakagawa,S. Sugahara","Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM",,"Solid-State Electron.",,"vol. 128","no. Supplement C","pp. 194-199",2016,Oct.
"Y. Shuto,S. Yamamoto,S. Sugahara","Energy Performance of Nonvolatile Power-Gating SRAM Using SOTB Technology","46th European Solid-State Device Conference",,,,,,2016,Sept.
"Y. Shuto,S. Yamamoto,S. Sugahara","Design and Implementation of Nonvolatile Power-Gating SRAM Using SOTB Technology","International Symposium on Low Power Electronics and Design, San Francisco",,,,,,2016,Aug.
"Y. Shuto,S. Yamamoto,S. Sugahara","Nonvolatile Power-gating Architecture for SRAM using SOTB Technology","016 IEEE Silicon Nanoelectronics Workshop (SNW 2016)",,,,,,2016,June
"Y. Shuto,S. Yamamoto,S. Sugahara","New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM","29th IEEE International Conference on Microelectronic Test Structures (ICMTS)",,," 8-1",,,2016,Mar.
"Y. Takamura,Y. Shuto,S. Yamamoto,H. Funakubo,M.K. Kurosawa,S. Nakagawa,S. Sugahara","Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAMs","2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)",,,,"pp. 72-75",2016,Jan.
"Sugahara, S.,Shuto, Y.,Shuichiro Yamamoto","Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems",,"Nanomagnetic Devices and Phenomena for Energy-Efficient Computing",,,,"pp. 65-90",2016,
"Yusuke Shuto,Shuu'ichirou Yamamoto,Satoshi Sugahara","Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology","18th Design, Automation and Test in Europe (DATE15)",,,,,,2015,Mar.
"Shuto, Y.,Shuichiro Yamamoto,Sugahara, S.","Quantitative comparison of power-gating architectures for FinFET-based nonvolatile SRAM using spintronics retention technology",,"2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings",,,,,2015,
"R. Nakane,Y. Shuto,H. Sukegawa,Z.C. Wen,S. Yamamoto,S. Mitani,M. Tanaka,K. Inomata,S. Sugahara","Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip",,"Solid-State Electronics","Elsevier","Vol. 102",,"pp. 52-58",2014,Dec.
"Yusuke Shuto,Shuu'ichirou Yamamoto,Satoshi Sugahara","Comparative Study of Power-Gating Architectures for Nonvolatile SRAM Cells Based on Spintronics Technology","2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2014)",,,,,,2014,Nov.
"Yusuke Shuto,Shuu'ichirou Yamamoto,Satoshi Sugahara","Near-threshold voltage operation of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture","2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S Conference 2014)",,,,,,2014,Oct.
"Satoshi Sugahara,Yota Takamura,Yusuke Shuto,Shuu’ichirou Yamamoto","Field-Effect Spin-Transistors",,"Handbook of Spintronics","Springer Netherlands",,,"pp. 1-31",2014,Oct.
"Yusuke Shuto,Shuu'ichirou Yamamoto,Satoshi Sugahara","0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture","2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2014)",,,,,,2014,Sept.
"Y. Shuto,S. Yamamoto,S. Sugahara","Design and performance of nonvolatile SRAM cells based on pseudo-spin-FinFET architecture","2014 IEEE Silicon Nanotechnology Workshop (SNW2014)",,,,,,2014,June
"周藤 悠介,Shuichiro Yamamoto,介川 裕章,Wen ZhenChao,中根 了昌,三谷 誠司,田中 雅明,猪俣 浩一郎,菅原 聡","ナノCMOSデバイスを用いた擬似スピンMOSFETの設計と性能 (シリコン材料・デバイス・IEDM特集(先端CMOSデバイス・プロセス技術))",,"電子情報通信学会技術研究報告 : 信学技報","一般社団法人電子情報通信学会","Vol. 112","No. 421","pp. 43-46",2013,Jan.
"Nakane, R.,Shuto, Y.,Sukegawa, H.,Wen, Z.C.,Shuichiro Yamamoto,Mitani, S.,Tanaka, M.,Inomata, K.,Sugahara, S.","Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service",,"European Solid-State Device Research Conference",,,,"pp. 272-275",2013,
"Shuichiro Yamamoto,Shuto, Y.,Sugahara, S.","Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic",,"EPJ Applied Physics",,"Vol. 63","No. 1",,2013,
"Shuto, Y.,Shuichiro Yamamoto,Sugahara, S.","FinFET-based pseudo-spin-transistor: Design and performance",,"2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013",,,,,2013,
"S. Sugahara,Y. Shuto,S. Yamamoto","Energy-efficient nonvolatile logic systems based on CMOS/spintronics hybrid technology","the 222nd Meeting of the Electrochemical Society / the 2012 Pacific Rim Meeting on Electrochemical and Solid-Sate Science (PRIME)",,,,,,2012,Oct.
"SATOSHI SUGAHARA,Yusuke Shuto,Shuu'ichirou Yamamoto","スピントロニクス/CMOS融合技術:スピントランジスタ・アーキテクチャ","平成24年秋季 第73回応用物理学会学術講演会",,,,,,2012,Sept.
"Shuu'ichirou Yamamoto,Yusuke Shuto,SATOSHI SUGAHARA","擬似スピンMOSFET技術を用いたFPGAの不揮発性パワーゲーティング","平成24年秋季 第73回応用物理学会学術講演会",,,,,,2012,Sept.
"Shuu'ichirou Yamamoto,Yusuke Shuto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性DFF：BETにおける静的リーク電流の影響","平成24年秋季 第73回応用物理学会学術講演会",,,,,,2012,Sept.
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAM:スリープモード動作とその応用","平成24年秋季 第73回応用物理学会学術講演会",,,,,,2012,Sept.
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAMのスタティックノイズマージンとエネルギー性能の解析","電子通信学会集積回路研究会(ICD)シリコン材料・デバイス研究会(SDM)共催研究会",,,,,,2012,Aug.
"菅原聡,周藤悠介,山本修一郎","スピントロニクス/CMOS融合技術: スピン機能MOSFETとその低消費電力ロジック応用","半導体・集積回路技術シンポジウム",,,,,,2012,July
"Y. Shuto,S. Yamamoto,S. Sugahara","Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs","2012 IEEE Silicon Nanotechnology Workshop (SNW2012)",,,,,,2012,June
"Y. Shuto,S. Yamamoto,S. Sugahara","Static noise margin and power-gating efficiency of a new nonvolatile SRAM cell based on pseudo-spin-transistor architecture","4th IEEE Int. Memory Technology Workshop (IMW2012)",,,,,,2012,May
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAM:スタティックノイズマージン評価","第59回応用物理学関係連合講演会",,,,,,2012,Mar.
"林 明日香,Shuichiro Yamamoto,前島 英雄","マルチメディア処理に向けたリコンフィギュラブルプロセッサの実現と評価 (コンピュータシステム)",,"電子情報通信学会技術研究報告 : 信学技報","一般社団法人電子情報通信学会","Vol. 111","No. 398","pp. 73-76",2012,Jan.
"林 明日香,Shuichiro Yamamoto,前島 英雄","マルチメディア処理に向けたリコンフィギュラブルプロセッサの実現と評価 (VLSI設計技術)",,"電子情報通信学会技術研究報告 : 信学技報","一般社団法人電子情報通信学会","Vol. 111","No. 397","pp. 73-76",2012,Jan.
"林 明日香,Shuichiro Yamamoto,前島 英雄","マルチメディア処理に向けたリコンフィギュラブルプロセッサの実現と評価",,"電子情報通信学会技術研究報告. VLD, VLSI設計技術",,"Vol. 111","No. 397","pp. 73-76",2012,Jan.
"林 明日香,Shuichiro Yamamoto,前島 英雄","マルチメディア処理に向けたリコンフィギュラブルプロセッサの実現と評価",,"電子情報通信学会技術研究報告. CPSY, コンピュータシステム",,"Vol. 111","No. 398","pp. 73-76",2012,Jan.
"林 明日香,Shuichiro Yamamoto,前島 英雄","マルチメディア処理に向けたリコンフィギュラブルプロセッサの実現と評価",,"電子情報通信学会技術研究報告. RECONF, リコンフィギャラブルシステム : IEICE technical report",,"Vol. 111","No. 399","pp. 73-76",2012,Jan.
"林 明日香,Shuichiro Yamamoto,前島 英雄","マルチメディア処理に向けたリコンフィギュラブルプロセッサの実現と評価 (リコンフィギャラブルシステム)",,"電子情報通信学会技術研究報告 : 信学技報","一般社団法人電子情報通信学会","Vol. 111","No. 399","pp. 73-76",2012,Jan.
"Shuto, Y.,Shuichiro Yamamoto,Sukegawa, H.,Wen, Z.C.,Nakane, R.,Mitani, S.,Tanaka, M.,Inomata, K.,Sugahara, S.","Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices",,"Technical Digest - International Electron Devices Meeting, IEDM",,,,"pp. 29.6.1-29.6.4",2012,
"十山 圭介,久保田 瞬,Shuichiro Yamamoto,前島 英雄","マルチコアでのメディア処理におけるプロセッサ動作時消費エネルギー低減方式の提案",,"映像情報メディア学会誌","一般社団法人映像情報メディア学会","Vol. 66","No. 3","pp. J74-J84",2012,
"Shuichiro Yamamoto,Shuto, Y.,Sugahara, S.","Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications",,"IEEE 2012 International Semiconductor Conference Dresden-Grenoble, ISCDG 2012",,,,"pp. 17-20",2012,
"Shuichiro Yamamoto,Shuto, Y.,Sugahara, S.","Nonvolatile power-gating FPGA based on pseudo-spin-transistor architecture with spin-transfer-torque MTJs",,"Materials Research Society Symposium Proceedings",,"Vol. 1430",,"pp. 55-60",2012,
"Shuichiro Yamamoto,Shuto, Y.,Sugahara, S.","Nonvolatile power-gating field-programmable gate array using nonvolatile static random access memory and nonvolatile flip-flops based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions",,"Japanese Journal of Applied Physics",,"Vol. 51","No. 11 PART2",,2012,
"Y. Shuto,S. Yamamoto,S. Sugahara","Evaluation and control of break-even time of nonvolatile SRAM based on spin-transistor architecture with spin-transfer-torque MTJs",,"J. Appl. Phys.",,"vol. 51","no. 4","pp. 040212/1-3",2012,
"Y. Shuto,S. Yamamoto,S. Sugahara","Nonvolatile SRAM based on spin-transistor architecture for nonvolatile power-gating systems","International Symposium on Advanced Hybrid Nano Devices (IS-AHND): Prospects by World’s Leading Scientists",,,,,,2011,Oct.
"S. Yamamoto,Y. Shuto,S. Sugahara","Nonvolatile power-gating FPGAs based on spin-transistor architecture","International Symposium on Advanced Hybrid Nano Devices (IS-AHND): Prospects by World’s Leading Scientists",,,,,,2011,Oct.
"SATOSHI SUGAHARA,Yusuke Shuto,Shuu'ichirou Yamamoto","CMOS/スピントロニクス融合技術による不揮発性ロジックシステムの展望","電子情報通信学会技術研究報告「磁気記録・情報ストレージ」",,,,,"pp. 63-70",2011,Oct.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","抵抗変化素子を用いたばらつき補償CMOSゲート","2010年春季 第57回応用物理学関係連合講演会",,,,,,2011,Sept.
"S. Yamamoto,Y. Shuto,S. Sugahara","Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems",,"IET Electronics Letters",,"vol. 47","no. 18","pp. 1027-1029",2011,Sept.
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAM：スリープ時リーク電流削減効果","第72回秋季応用物理学会学術講演会",,,,,,2011,Aug.
"Y. Shuto,S. Yamamoto,S. Sugahara","Evaluation and control of break-even time for nonvolatile SRAM using pseudo-spin-MOSFETs wit spin-transfer-torque MTJs","IEEE International Magnetics Conference 2011 (INTERMAG)",,,,,,2011,Apr.
"S. Yamamoto,Y. Shuto,S. Sugahara","Application of NV-DFF and NV-SRAM using spin-transistor Architecture with spin transfer torque MTJs to nonvolatile power-gating FPGA","IEEE International Magnetics Conference 2011 (INTERMAG)",,,,,,2011,Apr.
"S. Yamamoto,Y. Shuto,S. Sugahara","Power-gating ability and power aware design of nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs","IEEE International Magnetics Conference 2011 (INTERMAG)",,,,,,2011,Apr.
"SATOSHI SUGAHARA,Yusuke Shuto,Shuu'ichirou Yamamoto","CMOS/スピントロニクス融合技術による不揮発性ロジックシステムの展望",,"Magnetics Jpn.",,"vol. 6","no. 1","pp. 5-15",2011,
"Shuu'ichirou Yamamoto,Yusuke Shuto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAMと不揮発性DFFのFPGA応用","2010年秋季 第71回応用物理学会学術講演会",,,,,,2010,Sept.
"Shuu'ichirou Yamamoto,Yusuke Shuto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性DFF：静的リーク電流とBETの削減","2010年秋季 第71回応用物理学会学術講演会",,,,,,2010,Sept.
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAM：セルリーク電流とBETの削減","2010年秋季 第71回応用物理学会学術講演会",,,,,,2010,Sept.
"SATOSHI SUGAHARA,Yusuke Shuto,Shuu'ichirou Yamamoto","不揮発性メモリ素子を用いた不揮発性/ばらつき補償SRAM技術","2010年秋季第71回応用物理学会学術講演会",,,,,,2010,Sept.
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAM：ストア時の書き込み電流制御","2010年秋季 第71回応用物理学会学術講演会",,,,,,2010,Sept.
"Y. Shuto,S. Yamamoto,S. Sugahara","Operating analysis of nonvolatile SRAM using pseudo-spin-MOSFETs","The 6th International Conference on the Physics and Applications of Spin Related Phenomena in Semiconductors",,,,,,2010,Aug.
"Y. Shuto,R. Nakane,W. H. Wang,H. Sukegawa,S. Yamamoto,M. Tanaka,K. Inomata,S. Sugahara","A new spin-functional MOSFET based on MTJ technology: Pseudo-spin-MOSFET","The 6th International Conference on the Physics and Applications of Spin Related Phenomena in Semiconductors",,,,,,2010,Aug.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","抵抗変化素子を用いたばらつき補償CMOSゲート","2010年春季 第57回応用物理学関係連合講演会",,,,,,2010,Mar.
"Yusuke Shuto,Ryosyo Nakane,Wenhong Wang,介川裕章,Shuu'ichirou Yamamoto,Masaaki Tanaka,猪俣浩一郎,SATOSHI SUGAHARA","擬似スピンMOSFETの作製と評価","2010年春季 第57回応用物理学関係連合講演会",,,,,,2010,Mar.
"鈴木 邦彦,Shuichiro Yamamoto,前島 英雄","マルチコア向け統合開発環境におけるデバッグ効率向上のための視覚化機能の開発",,"全国大会講演論文集",,"Vol. 72",,"pp. 559-560",2010,Mar.
"Y. Shuto,S. Yamamoto,S. Sugahara","Operating analysis of nonvolatile SRAM using pseudo-spin-MOSFETs","11th Joint MMM-Intermag Conference",,,,,,2010,Jan.
"S Yamamoto,Satoshi Sugahara","Nonvolatile delay flip-flop using pseudo-spin-MOSFETs and its power-gating applications","the 11th Joint MMM/Intermag Conf.",,,,,,2010,Jan.
"S. Yamamoto,Satoshi Sugahara","Nonvolatile Delay Flip-Flop Based on Spin-Transistor Architecture and Its Power-Gating Applications",,"Jpn. J. Appl. Phys.",,"vol. 49","no. 9","pp. 090204/1-3",2010,
"Shuu'ichirou Yamamoto,Yusuke Shuto,Satoshi Sugahara","Nonvolatile SRAM (NV-SRAM) Using Resistive Switching Devices: Variable-Transconductance MOSFET Approach",,"Jpn. J. Appl. Phys",,"vol. 49","no. 4","pp. 040209/1-3",2010,
"Y. Shuto,R. Nakane,W. H. Wang,H. Sukegawa,S. Yamamoto,M. Tanaka,K. Inomata,S. Sugahara","A New Spin-Functional Metal-Oxide-Semiconductor Field-Effect Transistor Based on Magnetic Tunnel Junction Technology: Pseudo-Spin-MOSFET",,"Appl. Phys. Exp.",,"vol. 3","no. 1","pp. 013003/1-3",2010,
"S. Yamamoto,Yusuke Shuto,Satoshi Sugahara","Nonvolatile power-gating microprocessor concepts using nonvolatile SRAM and flip-flop","International Symposium on Silicon Nano Devices in 2030",,,,," P-50",2009,Oct.
"Y. Shuto,R. Nakane,H. Sukegawa,S. Yamamoto,M. Tanaka,K. Inomata,S. Sugahara","Fabrication and characterization of pseudo-spin-MOSFETs","Intl. Conf. Silicon Nano Devices in 2030",,,," paper P-49","pp. 148-149",2009,Oct.
"Y. Shuto,S. Yamamoto,S. Sugahara","Analysis and design of nonvolatile SRAM using spintronics technology","Non-volatile Memory Technology Symposium 2009 (NVMTS09)",,,,," paper P7",2009,Oct.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性DFF：バルーンDFFとの比較","第70回応用物理学会学術講演会",,," 10a-TA-6"," II分冊","p. 790",2009,Sept.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA,Hideo Maejima","マイクロプロセッサにおけるエマージングメモリデバイスへの期待","第70回応用物理学会学術講演会",,," 9p-TA-4"," 0分冊","p. 53",2009,Sept.
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","Spin-RAM/ReRAM技術を用いた機能MOSFETとその不揮発性SRAM/フリップフロップへの応用","平成21年秋季 第70回応用物理学会学術講演会",,,,," paper 9p-TA-8",2009,Sept.
"Yusuke Shuto,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAM：電源遮断動作消費電力の評価","平成21年秋季 第70回応用物理学会学術講演会",,,,," paper 10a-TA-5",2009,Sept.
"SATOSHI SUGAHARA,Yusuke Shuto,Shuu'ichirou Yamamoto","スピン機能MOSFETによる不揮発性ロック 不揮発性パワーゲーティング・ロジックへの応用 不揮発性SRAM/フリップフロップの可能性を検証",,"Semiconductor FPD World",,,,"pp. 46-49",2009,Sept.
"Shuu’ichirou.Yamamoto,Yusuke Shuto,Satoshi Sugahara","Nonvolatile SRAM(NV-SRAM) Using Functional MOSFET Merged with Resistive Switching Devices","Proceedings of IEEE 2009 Custom Integrated Circuits Conference (CICC)",,,,,"pp. 531-534",2009,Sept.
"Shuu’ichirou Yamamoto,Satoshi Sugahara","Nonvolatile delay flip-flop using magnetic tunnel junctions with current-induced magnetization switching architecture","IEEE International Magnetics Conference",,,,," ET-01",2009,May
"Yasuo Miyake,Shuu'ichirou Yamamoto,Hideo Maejima","マスタ・スレーブ型マルチプロセッサにおける動的可変優先度バス制御方式とその評価",,"電子情報通信学会論文誌",,"Vol. J92-C","No. 5","pp. 166-175",2009,May
"Y. Shuto,S. Yamamoto,S. Sugahara","Analysis and Design of Nonvolatile SRAM Using MOSFET-Based Spin-Transistors","Intermag 2009",,,," paper CT-02","p. 195",2009,May
"Shuu'ichirou Yamamoto,Satoshi Sugahara","Nonvolatile SRAM and flip-flop architectures using magnetic tunnel junctions with current-induced magnetization switching technology",,"Jpn. J. Appl. Phys.",,"Vol. 48","No. 4","pp. 043001-1-7",2009,Apr.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","スピン注入磁化反転MTJを用いた不揮発性Dフリップフロップ","第56回応用物理学関係連合講演会","第56回応用物理学関係連合講演会予稿集",,"Vol. 2",,"p. 785 1p-TB-6",2009,Apr.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","ノンポーラ型抵抗変化素子のSPICEモデル","第56回応用物理学関連連合講演会","第56回応用物理学関連連合講演会予稿集",,,," paper 2a-P16-13",2009,Mar.
"SATOSHI SUGAHARA,周藤悠介,Shuu'ichirou Yamamoto","抵抗変化素子を用いたFunctional MOSFET/CMOS","第56回応用物理学関連連合講演会",,,,," paper 2a-P16-14",2009,Mar.
"Shuu'ichirou Yamamoto,周藤悠介,SATOSHI SUGAHARA","ノンポーラ型抵抗変化素子を用いた不揮発性SRAM","第56回応用物理学関連連合講演会",,,,," paper 2a-P16-15",2009,Mar.
"周藤悠介,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","Pseudo-spin-MOSFETを用いた不揮発性SRAM：情報ストア動作解析","第56回応用物理学関連連合講演会",,,,," paper 1p-TB-8",2009,Mar.
"周藤悠介,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","擬似スピンMOSFETを用いた不揮発性SRAMの提案と解析","第13回半導体スピン工学の基礎と応用(PASPS-13)",,,," paper E-4","p. 42",2009,Jan.
"Y. Shuto,S. Yamamoto,S. Sugahara","Variability-Tolerant CMOS Gates Using Functional MOSFETs with Resistive Switching Devices","Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials",,,,,"pp. 810-811",2009,
"Yusuke Shuto,Shuu'ichirou Yamamoto,Satoshi Sugahara","Nonvolatile SRAM architecture using MOSFET-based spin-transistors",,"J. Appl. Phys.",,"Vol. 105",,"pp. 07C933/1-3",2009,
"Shuu'ichirou Yamamoto,Yusuke Shuto,SATOSHI SUGAHARA","スピン機能CMOSによる不揮発性高機能・高性能ロジック",,"スピントロニクスの基礎と材料・応用技術の最前線","シーエムシー出版",," 27章","pp. 319-330",2009,
"S. Yamamoto,S. Sugahara","Nonvolatile Static Random Access Memory (NV-SRAM) Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture",,"Jpn. J. Appl. Phys.",,"vol. 48","no. 4","pp. 043001/1-7",2009,
"S. Yamamoto,S. Sugahara","Analysis and design of nonvolatile SRAM using magnetic tunnel junctions with current-induced magnetization switching technology","53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008)",,,," paper CT-04","p. 196",2008,Nov.
"Y. Shuto,S. Yamamoto,S. Sugahara","Novel nonvolatile SRAM architecture using MOSFET-based spin-transistors",,"53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008)",,," paper CT-02","p. 195",2008,Nov.
"SATOSHI SUGAHARA,周藤悠介,Shuu'ichirou Yamamoto","スピン機能MOSFETによるスピントランジスタ・エレクトロニクス","応用物理学会応用電子物性分科会・スピントロニクス研究会共同主催研究会",,,," paper (5)","pp. 136-141",2008,Oct.
"SATOSHI SUGAHARA,周藤悠介,Shuu'ichirou Yamamoto","スピン機能MOSFETを用いた不揮発性高機能・高性能ロジック","応用物理学会応用電子物性分科会・スピントロニクス研究会例会","応用電子物性分科会誌",,"Vol. 14",,"pp. 136-141",2008,Oct.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","スピン注入磁化反転MTJを用いた不揮発性SRAM：通常動作時消費電力の削減","第69回応用物理学会学術講演会","第69回応用物理学会学術講演会予稿集",,"Vol. 2",,"p. 667 5a-R-11",2008,Sept.
"Yasuo Miyake,Shuu'ichirou Yamamoto,Hideo Maejima","マスタ・スレーブ型マルチプロセッサにおける動的可変優先度バス制御方式とその評価","2008年電子情報通信学会エレクトロニクスソサイエティ大会","2008年電子情報通信学会エレクトロニクスソサイエティ大会予稿集",,,,"p. C-12-33",2008,Sept.
"Satoshi Sugahara,Yota Takamura,Ryosyo Nakane,Yusuke Shuto,Shuu'ichirou Yamamoto","スピンMOSFET を用いたスピントランジスタ・エレクトロニクス","第69回応用物理学会学術講演会",,,,," paper 3p-E-3",2008,Sept.
"周藤悠介,Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","Pseudo-spin-MOSFETを用いた不揮発性SRAM：消費電力削減の効果","第69回応用物理学会学術講演会","第69回応用物理学会学術講演会予稿集",,"Vol. 2",,"p. paper 5a-R-12",2008,Sept.
"Satoshi Sugahara,Shuu'ichirou Yamamoto","Operating analysis of pseudo-spin-MOSFETs using MTJ with current-induced magnetization switching","The 55th Spring Meeting, 2008; The Japan Society of Applied Physics and Related Scieties","Extended Abstracts (The 55th Spring Meeting, 2008); The Japan Society of Applied Physics and Related Scieties",,,,"p. 30p-F-6",2008,Mar.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","スピン注入磁化反転MTJを用いた不揮発性SRAM：Vhalfの影響","第55回応用物理学会関連連合講演会",,,,," paper 30p-F-8",2008,Mar.
"Shuu'ichirou Yamamoto,SATOSHI SUGAHARA","スピン注入磁化反転MTJを用いた不揮発性SRAM：仮想接地セルアーキテクチャ","第55回応用物理学会関連連合講演会",,,,," paper 30p-F-7",2008,Mar.
"S. Yamamoto,S. Sugahara","Nonvolatile SRAM and flip-flop architectures using magnetic tunnel junctions with current-induced magnetization switching technology","52nd Annual Conf. on Magnetism and Magnetic Materials","52nd Annual Conf. on Magnetism and Magnetic Materials",,,,"p. 481 paper HP-02",2007,Nov.
"Shuu'ichirou Yamamoto,Satoshi Sugahara","Proposal and theoretical analysis of pseudo spin-MOSFETs using MTJ devices","The 68th Autumn Meeting, 2007; The Japan Society of Applied Physics","Extended Abstracts (The 68th Autumn Meeting, 2007); The Japan Society of Applied Physics",,"vol. 1",,"p. 496",2007,Sept.
"Shuu'ichirou Yamamoto,Satoshi Sugahara","Application of pseudo spin-MOSFET/spin-MOSFET for non-volatile SRAM/latch circuits","The 68th Autumn Meeting, 2007; The Japan Society of Applied Physics","Extended Abstracts (The 68th Autumn Meeting, 2007); The Japan Society of Applied Physics",,"vol. 1",,"p. 496",2007,Sept.
"Shuu'ichirou Yamamoto,Satoshi Sugahara","Non-volatile SRAM/latch circuits using MTJ devices with spin transfer torque magnetization switching","The 68th Autumn Meeting, 2007; The Japan Society of Applied Physics","Extended Abstracts (The 68th Autumn Meeting, 2007); The Japan Society of Applied Physics",,,,"p. 7p-S-18",2007,Sept.
"Hyun-Soo Kim,Shuu'ichirou Yamamoto,Toru Ishikawa,Takaaki Fuchikami,Hiroshi Ohki,Hiroshi Ishiwara","Fabrication and Characterization of 1k-bit 1T2C-Type Ferroelectric Memory Cell Array",,"Japanese Journal of Applied Physics",,"Vol. 44","No. 4B","pp. 2715-2721",2005,Apr.
"加藤潤三,MOTOSHI SAEKI,大西淳,古宮誠一,Shuichiro Yamamoto,Haruhiko Kaiya","シソーラスを用いた要求分析法","電子情報通信学会技術研究報告ソフトウェアサイエンス研究会","電子情報通信学会技術研究報告ソフトウェアサイエンス研究会",,"Vol. 104","No. 722","pp. 31-36",2005,Mar.
"Shuu'ichirou Yamamoto","1T2C型強誘電体メモリアレイにおけるV/4データ書き込み法の提案",,"第51回応用物理学関係連合講演会講演予稿集",,"Vol. 2",,"pp. 625",2004,
"Shuu'ichirou Yamamoto","Fabrication and Characterization of 1k-bit 1T2C-Type Ferroelectric Memory Cell Array",,"Extended Abstract of the 2004 International Conference on Solid State Devices and Materials",,,,"pp. 54-55",2004,
"Shuu'ichirou Yamamoto","Improved Data Disturbance Effects in 1T2C-Type Ferroelectric Memory Array",,"Japanese Journal of Applied Physics",,"Vol. 43",,"pp. 2558-2563",2004,
"S. Yamamoto,T. Ishikawa,T.Fuchikami,H. Kim,K. Aizawa,B. Park,T. Furukawa,H. Ohki,S. Kikuchi,H. Hoko,H. Ishiwara","Fabrication of 1K-Bit 1T2C-Type Ferroelectric Memory Cell Array",,"Symposium Abstracts (The 16th International Symposium on Integrated Ferroelectrics)",,,,"pp. 5-01-P",2004,
"Shuu'ichirou Yamamoto","Improvement of Data Readout Disturbance Effects in 1T2C-Type Ferroelectric Memory Array",,"Symposium Abstracts (The 16th International Symposium on Integrated Ferroelectrics) ",,,,,2004,
"HYUN-SOO KIM,SHUU'ICHIROU YAMAMOTO,HIROSHI ISHIWARA","Improvement of Data Readout Disturbance Effect in 1T2C-Type Ferroelectric Memory Array",,"Integrated Ferroelectrics",,"Vol. 67",,"pp. 271-280",2004,
"金?秀,Shuu'ichirou Yamamoto,石川徹,大木博,HIROSHI ISHIWARA","1T2C型強誘電体メモリアレイの作製と評価",,"第65回応用物理学会学術講演会講演予稿集",,"Vol. 2",,"pp. 496",2004,
"SHUU'ICHIROU YAMAMOTO,TORU ISHIKAWA,TAKAAKI FUCHIKAMI,HYUN-SOO KIM,KOUJI AIZAWA,BYUNG-EUN PARK,TAISUKE FURUKAWA,HIROSHI OHKI,SHIN KIKUCHI,HIROMASA HOKO,HIROSHI ISHIWARA","Fabrication of 1K-Bit 1T2C-Type Ferroelectric Memory Cell Array",,"Integrated Ferroelectrics",,"Vol. 67",,"pp. 281-286",2004,
"Juzo Kato,Motoshi Saeki,Atsushi Ohnishi,Morio Nagata,Haruhiko Kaiya,Seiichi Komiya,Shuichiro Yamamoto,Hisayuki Horai,Kenji Watahiki","PAORE: Package Oriented Requirements Elicitation",,"Proc. of 10th Asia-Pacific Software Engineering Conference (APSEC2003)",,,,"pp. 17-26",2003,Dec.
"加藤潤三,MOTOSHI SAEKI,大西淳,永田守男,Haruhiko Kaiya,古宮誠一,Shuichiro Yamamoto,綿引健二,蓬莱尚幸","要求分析のためのシソーラス作成支援",,"電子情報通信学会技術研究報告知能ソフトウェア工学KBSE2003-5?12",,"Vol. 103","No. 217","pp. 41-46",2003,June
"金泫季,山本修一郎,石原宏","1T2C型強誘電体メモリにおけるデータディスターブの解析と低減法の提案",,"電子情報通信学会技術報告",,"Vol. 102","No. 732","pp. 19",2003,
"Shuu'ichirou Yamamoto","Fabrication of 1T2C-Type Ferroelectric Memory Array with Sense Amplifiers",,"Journal of Conference Abstracts",,"Vol. 8","No. 1","pp. 363",2003,
"石川徹,山本修一郎,石原宏","SPICEによる1T2C型強誘電体メモリアレイの動作解析",,"第50回応用物理学関係連合講演会講演予稿集",,"Vol. 2",,"pp. 609",2003,
"タンブンイー,斉藤亮平,山本修一郎,石原宏","強誘電体を用いた不揮発性ＣＭＯＳラッチ回路の特性評価",,"第64回応用物理学会学術講演会講演予稿集",,"Vol. 2",,"pp. 475",2003,
"金泫季,山本修一郎,石原宏","1Ｔ2Ｃ型強誘電体メモリセルに対する読み出しディスターブの低減法",,"第64回応用物理学会学術講演会講演予稿集",,"Vol. 2",,"pp. 476",2003,
"Shuu'ichirou Yamamoto","1Ｔ2Ｃ型強誘電体メモリアレイの読み出し回路の設計と評価",,"第64回応用物理学会学術講演会講演予稿集",,"Vol. 2",,"pp. 476",2003,
"Toru Ishikawa,Shuu’ichirou Yamamoto,Takaaki Fuchikami,Taisuke Furukawa,Kouji Aizawa,Byung-Eun Park,Shin Kikuchi,Hiroshi Ohki,Hiromasa Hoko,Hiroshi","Fabrication of 1T2C-Type Ferroelectric Memory Cell Array",,"Book of Abstracts (15th International Conference on Integrated Ferroelectrics)",,,,"pp. 242",2003,
"Xusheng Wang,Shuu’ichirou Yamamoto,Hiroshi Ishiwara","Low Temperature Synthesis of SrBi2Ta2O9 Thin Films with Bi2SiO5-Containing Seed Layers",,"Japanese Journal of Applied Physics ",,"Vol. 41",,"pp. L1492",2003,
"Shuu'ichirou Yamamoto,Hyun-Soo Kim,Hiroshi Ishiwara","Proposal of a Planar 8F2 1T2C-Type Ferroelectric Memory Cell",,"Japanese Journal of Applied Physics",,"Vol. 42",,"pp. 2059-2062",2003,
"Hyun-soo Kim,Shuu’ichirou Yamamoto,Hiroshi Ishiwara","Operation Simulation of an 8F2 1T2C-Type Ferroelectric Memory Array with a Revised Data Writing Method",,"Book of Abstracts (15th International Conference on Integrated Ferroelectrics)",,,,"pp. 228",2003,
"金泫季,山本修一郎,石原宏","1T2C型強誘電体メモリアレイに対するデータ書き込みディスターブの低減法",,"第50回応用物理学関係連合講演会講演予稿集",,"Vol. 2",,"pp. 609",2003,
"Shuu'ichirou Yamamoto","強誘電体を用いた不揮発性CMOSラッチ回路の消費電力の評価",,"第50回応用物理学関係連合講演会講演予稿集",,"Vol. 2",,"pp. 609",2003,
"Shuu'ichirou Yamamoto","Operation Simulation of an 8F2 1T2C-Type Ferroelectric Memory Array with a Revised Data Writing Method",,"Integrated Ferroelectrics",,"Vol. 56",,"pp. 1045-1054",2003,
"加藤潤三,MOTOSHI SAEKI,大西淳,永田守男,Haruhiko Kaiya,古宮誠一,Shuichiro Yamamoto,綿引健二,蓬莱尚幸","PAORE : パッケージ指向の要求獲得プロセス",,"電子情報通信学会技術研究報告知能ソフトウェア工学KBSE2002-13?20",,"Vol. 102","No. 503","pp. 25-30",2002,Dec.
"Hiroshi Ishiwara,Shuu'ichirou Yamamoto","A Novel Data Writing Method in a 1T2C-Type Ferroelectric Memory",,"Proceedings of the 23rd International Conference on Microelectronics",,"Vol. 2",,"pp. 517-520",2002,
"Shuu'ichirou Yamamoto,Susumu Inoue,Hiroshi Ishiwara","Analysis of non-volatile latch circuits with ferroelectric-gate field effect transistors for low power and low voltage operation",,"Proceedings of the 23rd International Conference on Microelectronics",,"Vol. 2",,"pp. 589-592",2002,
"Hiroshi Ishiwara,Shuu'ichirou Yamamoto","A novel data writing method in a 1T2C-type ferroelectric memory",,"Facta Universitatis (Nis) - Elec. Energ.",,"Vol. 15","No. 1","pp. 81-92",2002,
"山本修一郎,石原宏","FETのゲート容量を考慮した1T2C型強誘電体メモリの新規書込み法の提案と動作解析",,"第49回応用物理学関係連合講演会講演予稿集",,"Vol. 2",,"pp. 544",2002,
"山本修一郎,井上進,石原宏","不揮発性強誘電体ラッチ回路の新構成法と低電圧動作解析",,"電子情報通信学会技術報告",,"Vol. 101","No. 719","pp. 1-6",2002,
"金■玄秀,山本修一郎,石原宏","1T2C型強誘電体の高集積化とSPICEによる動作解析",,"第63回応用物理学会学術講演会講演予稿集",,"Vol. 2",,"pp. 448",2002,
"Shuu'ichirou Yamamoto,Hyun-Soo Kim,Hiroshi Ishiwara","Proposal of a planar 8F2 1T2C-type ferroelectric memory cell",,"Extended Abstract of the 2002 International Conference on Solid State Devices and Materials",,,,"pp. 622-623",2002,
"山本修一郎,金■玄秀,石原宏","1T2C型強誘電体メモリアレイにおける書込み・読出しデータディスターブ低減法",,"第63回応用物理学会学術講演会講演予稿集",,"Vol. 2",,"pp. 448",2002,
"Shuu'ichirou Yamamoto,Takumi Kato,Hiroshi Ishiwara","Novel Simulation Program with Integrated Circuit Emphasis (SPICE) Model of Ferroelectric Capacitors Using Schmitt Trigger Circuit",,"Japanese Journal of Applied Physics",,"Vol. 40","No. 4B","pp. 2928-2934",2001,
"井上進,山本修一郎,石原宏","強誘電体ゲートFETを用いた不揮発性ラッチ回路の動作解析",,"Extended Abstracts (The 48th Spring Meeting,2001)",,"Vol. 2",,"pp. 549",2001,
"山本修一郎,平山智久,石原宏","強誘電体キャパシタシミュレーション支援LSIの設計",,"電子情報通信学会2001年総合大会講演講演論文集・エレクトロニクス２",,,,"pp. 128",2001,
"山本修一郎,石原宏","強誘電体を用いた不揮発性CMOSラッチ回路の新構成法と低電圧動作解析",,"第62回応用物理学会学術講演会講演予稿集",,"Vol. 2",,"pp. 381",2001,
"平山智久,山本修一郎,石原宏","1T2C型強誘電体メモリの周辺回路の設計",,"電子情報通信学会2001年エレクトロニクスソサイエティ大会講演論文集２",,,,"pp. 97",2001,
"Shuu'ichirou Yamamoto,Shunri Oda","Atomic Layer-by-Layer MOCVD of Complex Metal Oxides and In Situ Process Monitoring",,"Chemical Vapor Deposition",,"Vol. 7","No. 1","pp. 7-18",2001,
"山本修一郎,石原宏","Building of Parallel-element Ferroelectric Capacitor Model Using Schmitt Trigger Circuit",,"Extended Abstracts (The 61th Autumn Meeting, 2000)",,,,"pp. 447",2000,
"Shuu'ichirou Yamamoto,Takumi Kato,Hiroshi Ishiwara","A Novel SPICE Model of Ferroelectric Capacitors Using Schmitt Trigger Circuit",,"Extended Abstract of the 2000 International Conference on Solid State Devices and Materials",,,,"pp. 270-271",2000,
"加藤匠,高原淳,山本修一郎,小笠原悟,徳光永輔,石原宏","HSPICE Simulation of Transistor-type Ferroelectric Memory",,"Extended Abstracts (The 47th Spring Meeting,2000)",,,,"pp. 541",2000,
"Shuu'ichirou Yamamoto,Kouji Nagata,Satoshi Sugai,Akio Sengoku,Yasunari Matsukawa,Takeo Hattori,Shunri Oda","Reproducible Growth of Metalorganic Chemical Vapor Deposition Derived YBa2Cu3OX Thin Films Using Ultrasonic Gas Concentration Analyzer",,"Japanese Journal of Applied Physics",,"Vol. 38",,"pp. 4727-4732",1999,
"S. Oda,S. Yamamoto,Z. Wang,H. Tobisaka,K. Nagata","ATOMIC LAYER MOCVD OF OXIDE SUPERCONDUCTORS AND DIELECTRICS",,"High-Temperature Superconductors and Novel Inorganic Materials, NATO ASI Series 3 (eds. by G. Van Tendeloo, E.V. Antipov and S.N. Putilin, Kluwer Academic, Dordorecht)","High-Temperature Superconductors and Novel Inorganic Materials, NATO ASI Series 3 (eds. by G. Van Tendeloo, E.V. Antipov and S.N. Putilin, Kluwer Academic, Dordorecht)","Vol. 62",,"pp. 75-78",1999,
"加藤匠,山本修一郎,石原宏","強誘電体の過渡応答SPICEモデル(II)",,"Extended Abstracts (The 60th Autumn Meeting, 1999)",,,,"pp. 461",1999,
"Shuu'ichirou Yamamoto,Satoshi Sugai,Yasunari Matsukawa,Akio Sengoku,Hiroshi Tobisaka,Takeo Hattori,Shunri Oda","In situ Growth Monitoring during Metalorganic Chemical Vapor Deposition of YBa2Cu3OX Thin Films by Spectroscopic Ellipsometry",,"Japanese Journal of Applied Physics",,"Vol. 38",,"pp. L632-L635",1999,
"Shuu'ichirou Yamamoto","原子層MOCVD法による高温超伝導薄膜デバイスに関する研究",,,,,,,1999,
"Shuu'ichirou Yamamoto,Shunri Oda","atomic controlled interface of superconductors",,"Extended Abstracts of Special Session for Superconducting Devices",,,,"pp. 25-30",1998,
"Shuu'ichirou Yamamoto,Tomotaka Watanabe,Shunri Oda","Junction Formation in YBaCuO Thin Films by Scanning Probe",,"Journal of Low Temperature Physics",,"Vol. 106",,"pp. 423-432",1997,
"Shuu'ichirou Yamamoto,Atsushi Kawaguchi,Shunri Oda","Anomalous Current-Voltage Characteristics along the c-Axis in YBaCuO Thin Films Prepared by MOCVD and AFM Lithography",,"Phisica C",,"Vol. 293",,"pp. 244-248",1997,
"Shuu'ichirou Yamamoto,Atsushi Kawaguchi,Kouji Nagata,Takeo Hattori,Shunri Oda","Atomic layer-by-layer epitaxy of oxide superconductors by MOCVD",,"Applied Surface Science",,"Vol. 112",,"pp. 30-37",1997,
"Shuu'ichirou Yamamoto,Atsushi Kawaguchi,Shunri Oda","Preparation of Thin Films of YBa2Cu3OX with a Smooth Surface by Atomic Layer MOCVD",,"Material Science of Engineering B",,"Vol. 41",,"pp. 87-92",1996,
"Shunri Oda,Hideaki Zama,Shuu'ichirou Yamamoto","Superconductivity and Surface Morphology of YBCO Thin Films Prepared by Metalorganic Chemical Vapor Deposition",,"IEEE Transaction of Applied Superconductor",,"Vol. 5",,"pp. 1801-1804",1995,
"Shuu'ichirou Yamamoto,Atsushi Kawaguchi,Shunri Oda","Critical Current Density of YBCO Ultra Thin Films Prepared by Atomic Layer MOCVD",,"Advances in Superconductivity VII (eds. by K.Ysmafuji and T.Morishita Springer, Tokyo)","Advances in Superconductivity VII (eds. by K.Ysmafuji and T.Morishita Springer, Tokyo)",,,"pp. 979-982",1995,
"Shuu'ichirou Yamamoto,Hideaki Suzuki,Tomotaka Watanabe,Atsushi Kawaguchi,Takeo Hattori,Shunri Oda","STM/AFM Fabricated Junctions of YBaCuO Films",,"Extended Abstracts of 5th International Superconductive Electronics Conference",,,,"pp. 93-95",1995,
"Shunri Oda,Shuu'ichirou Yamamoto,Atsushi Kawaguchi","Atomic Layer-by-Layer MOCVD of Oxide Superconductors",,"Journal de Physique IV",,"Vol. C5",,"pp. 379-390",1995,
"Shunri Oda,Hideaki Zama,Shuu'ichirou Yamamoto","Atomic layer controlled metalorganic chemical vapor deposition of superconducting YBa2Cu3OX films",,"Journal of Crystal Growth",,"Vol. 145",,"pp. 232-236",1994,
"Shunri Oda,Hideaki Zama,Shuu'ichirou Yamamoto","Atomic Layer Metalorganic Chemical Vapor Deposition of YBa2Cu3OX with In Situ Optical Reflectance Measurement",,"Proceedings of the 7th Topical Meeting on Crystal Growth Mechanism",,,,"pp. 285-290",1994,