"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Wei Deng,Zule Xu,Haosheng Zhang,Jian Pang,Yun Wang,Rui Wu,染谷 晃基,白根 篤史,岡田 健一","A 21.7% System Power Efficiency Fully-Synthesizable Transmitter for sub-GHz IoT Applications","電子情報通信学会 ソサイエティ大会",,,,,,2019,Sept.
"Junjun Qiu,Bangan Liu,Yuncheng Zhang,染谷 晃基,白根 篤史,岡田 健一","Digital Baseband Design for Sub-GHz Transceiver","電子情報通信学会 ソサイエティ大会",,,,,,2019,Sept.
"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Wei Deng,Zule Xu,Haosheng Zhang,Jian Pang,Yun Wang,Rui Wu,Teruki Someya,Atsushi Shirane,Kenichi Okada","An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator Based Frequency Synthesizer and Digital Background EVM Calibration","IEEE Custom Integrated Circuits Conference (CICC)",,,,,,2019,Apr.
"Bangan Liu,Yuncheng Zhang,Junjun Qiu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Fully-synthesizable Ring Oscillator Based Frequency Synthesizer for Sub-GHz IoT Application","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-112","No. 507","pp. 67-71",2019,Mar.
"Junjun Qiu,Bangan Liu,Yuncheng Zhang,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Fully-synthesizable Symbol Timing Recovery Circuit for Low-Power Wireless Receiver","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-113","No. 507","pp. 73-76",2019,Mar.
"Yuncheng Zhang,Bangan Liu,Junjun Qiu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A Low-Power Area Efficient Sub-GHz IoT Receiver without Off-Chip Components","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-114",,"pp. 77-80",2019,Mar.
"Bangan Liu,Huy Cu Ngo,Kengo Nakata,Wei Deng,Yuncheng Zhang,Junjun Qiu,Toru Yoshioka,Jun Emmei,Jian Pang,Tn Aravind,Haosheng Zhang,Dongsheng Yang,Hanli Liu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A 0.4ps-Jitter -52dBc-Spur Synthesizable Injection-locked PLL with Self-clocked Non-overlap Update and Slope-balanced Sub-sampling BBPD",,"IEEE Solid-State Circuits Letters (SSC-L)",,"Vol. 2","No. 1","pp. 5-8",2019,Jan.