"赤木佳乃,佐藤真平,高橋篤司","集合対間配線における目標端子対選択法に関する一検討","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2017-59)",,"Vol. 117","No. 273","pp. 235-240",2017,Nov.
"Atsushi Takahashi","Routing Algorithms - from classic to advanced -","IEEE CASS Central China Workshop",,,,,,2017,Nov.
"高橋篤司","FR とファンダム・レビュー",,"電子情報通信学会 基礎・境界ソサイエティ Fundamentals Review",,"Vol. 11","No. 2",,2017,Oct.
"西原明法,スチュワート デービッド,篭橋 雄二,高橋 篤司,山田 明","6大学人財交流による教員育成の推進","日本教育工学会 第33回全国大会","日本教育工学会 第33回全国大会 講演論文集",,,,,2017,Sept.
"Atsushi Takahashi","Routing Algorithms - from classic to advanced -","2017 Taiwan and Japan Conference on Circuits and Systems (TJCAS)",,,,,,2017,Aug.
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","An Idea for Maximizing Target Pin-Pair Connections in Set-Pair Routing",,"Proc. the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017)",,,,"pp. 62-65",2017,July
"Takeshi Ihara,Toshiyuki Hongo,Atsushi Takahashi,Chikaaki Kodama","A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E100-A","No. 7","pp. 1473-1480",2017,July
"右近祐太,佐藤真平,高橋篤司","演算器の可変レイテンシ化による処理性能と回路面積のトレードオフに関する評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2017-26)",,"Vol. 117","No. 97","pp. 119-124",2017,June
"高橋 篤司","IEEE CEDA日本チャプター発足とその役割","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2017-59)",,"Vol. 117","No. 17","pp. 31-34",2017,May
"赤木佳乃,佐藤真平,高橋篤司","目標端子対接続の実現を目指す集合対間配線アルゴリズム","第30回 回路とシステムワークショップ","第30回 回路とシステムワークショップ 論文集",,,,"pp. 180-185",2017,May
"杉原舜,佐藤真平,高橋篤司","単層プリント基板における目標等長配線を実現するための部分配線修正手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-114)",,"Vol. 116","No. 478","pp. 73-78",2017,Mar.
"高橋篤司","グラフは難だが役に立つ",,"電子情報通信学会 2017年総合大会 講演論文集 (AS-1-4)",,"Vol. A",,"pp. S6-S7",2017,Mar.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling",,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems",,"Vol. 25","No. 3","pp. 998-1011",2017,Mar.
"半田昌平,佐藤真平,高橋篤司","TPLのための半正定値計画緩和に基づくレイアウト分割手法のポリゴン集合クラスタリングによる高速化","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-111)",,"Vol. 116","No. 478","pp. 55-60",2017,Mar.
"尾頭篤,佐藤真平,高橋篤司","LELEダブルパターニングにおけるFMアルゴリズムを用いた効率的なパターン局所修正手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-113)",,"Vol. 116","No. 478","pp. 67-72",2017,Mar.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 10",,"pp. 28-38",2017,Feb.
"佐藤真平,右近祐太,高橋篤司","典型的な回路を用いた近似演算における入力系列の演算精度への影響の調査","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-95)",,"Vol. 116","No. 415","pp. 165-170",2017,Jan.