論文

• Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. HOG-Based Object Detection Processor Design Using ASIP Methodology, IEICE Trans. on Fundamentals, Vol. E100-A, No. 12, pp. 2972-2984, Dec. 2017.
• Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm, IEICE Trans. Fundamentals, Vol. E100-A, No. 7, pp. 1384-1395, July 2017.
• Zhiqiang Hu, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Narrow Fingerprint Template Synthesis by Clustering Minutiae Descriptors, IEICE Trans. Information and Systems, Vol. E100-D, No. 6, pp. 1290-1302, June 2017.
• Zhiqiang Hu, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Hybrid Minutiae Descriptor for Narrow Fingerprint Verification, IEICE Trans. Information and Systems, Vol. E100-D, No. 3, pp. 546-555, Mar. 2017.
• Hao Xiao, Ning Wu, Fen Ge, Tsuyoshi Isshiki, Hiroaki Kunieda, Jun Xu, Yuangang Wang. Efficient synchronization for distributed embedded multiprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 2, No. 4, pp. 779-783, Apr. 2016.
• Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. A Fast Trace Aware Statistical Based Prediction Model With Burst Traffic Modeling for Contention Stall In A Priority Based MPSoC Bus, IPSJ Trans. System LSI Design Methodology, Vol. 9, pp. 37-48, Feb. 2016.
• Hao Xiao, Busheng Zheng, Tsuyoshi Isshiki, Hiroaki Kunieda. Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer, IET Computers & Digital Techniques, Vol. 11, No. 1, pp. 8-15, Jan. 2016.
• Surachai Thongkaew, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Register-Based Process Virtual Machine Acceleration Using Hardware Extension with Hybrid Execution, IEICE Trans. Fundamentals, Vol. E98-A, No. 12, pp. 2505-2518, Dec. 2015.
• Surachai Thongkaew, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension, ISPJ Journal of Information Processing, Vol. 23, No. 3, pp. 118-130, Mar. 2015.
• ARIF ULLAH KHAN, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-Coupled Thread Model, IPSJ Trans. System LSI Design Methodology, Vol. 8, pp. 38-50, Feb. 2015.
• Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Retargeting Derivative-ASIP with Assembly Converter Tool, IEICE Trans. Information and Systems, The Institute of Electronics, Information and Communication Engineers, Vol. E97-D, No. 5, pp. 1188-1195, May 2014.  公式リンク  
  
• Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach, IPSJ Journal of Information Processing, Information Processing Society of Japan, Vol. 22, No. 2, pp. 131-141, Apr. 2014.  公式リンク  
  
• Hsuan Chun Liao, TSUYOSHI ISSHIKI, Mochamad Asri, DONGJU LI, hiroaki kunieda. A High Level Design of Reconfigurable and High-performance ASIP Engine for Image Signal Processing, IEICE Trans. Fundamentals, Vol. E95-A, No. 12, pp. 2373 - 2383, Dec. 2013.
• Hsuan Chun Liao, TSUYOSHI ISSHIKI, Mochamad Asri, DONGJU LI, hiroaki kunieda. A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine, IEICE Trans. Fundamentals, Vol. E96-A, No. 6, pp. 1222 - 1235, June 2013.
• Hsuan Chun Liao, Mochamad Asri, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda. Flexible and High Performance ASIPs for Pixel Level Image Processing Two Dimensional Image Processing, 情報処理学会論文誌, Vol. 54, No. 7, pp. 552 - 562, Feb. 2013.
• Hao Xiao, TSUYOSHI ISSHIKI, ARIF ULLAH KHAN, DONGJU LI, hiroaki kunieda. A Low-Cost and Energy-Effcient Multiprocessor System-on-Chip for UWB MAC Layer, IEICE Transaction on Information and Systems, Vol. E95-D, No. 8, Aug. 2012.
• Hao Xiao, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda, Yuko Nakase, Sadahiro Kimura. Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology, IPSJ Transactions on System LSI Design Methodology, IPSJ, Vol. 5, pp. 118 - 132, May 2012.
• SangWoo Sin; Dongju Li; Tsuyoshii Isshik; Hiroaki Kunieda, SangWoo Sin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Fingerprint Verification with Scratch Feature for Personal Device, Optical Engineering, Feb. 2012.
• Sang Woo Sin, Ru Zhou, DONGJU LI, TSUYOSHI ISSHIKI, hiroaki kunieda. Narrow Fingerprint Sensor Verification with Template Updating Technique, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E95-A, No. 1, pp. 346-353, Jan. 2012.
• Hao Ni, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Robust Multiple Minutiae Partitions for Distorted Fingerprint Matching, IEICE Transactions on Information and Systems, submitted, Nov. 2011.
• Ru Zhou, Sang Woo Sin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Ultrafast fingerprint indexing for embedded systems, Optical Engineering, SPIE, Oct. 2011.
• Yukun LIU, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA. Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems, IEICE transaction on Information and System, Vol. E94-D, No. 9, pp. 1792-1799, Sept. 2011.
• Hao Ni, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Unique Fingerprint-Image-Generation Algorithm for Line Sensors, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 2, pp. 781-788, Feb. 2011.
• ARIF ULLAH KHAN, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda. A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips, IPSJ Transactions on System LSI Design Methodology, 情報処理学会, Vol. 3, pp. 194 - 206, Aug. 2010.
• Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Orientation Field Extimation for Embedded Fingerprint Authentication System, IEICE transaction on Information and System, vol. E93-D, No. 7, pp. 1918 - 1926, July 2010.
• Mohammad Zalfany Urfianto, TSUYOSHI ISSHIKI, ARIF ULLAH KHAN, DONGJU LI, hiroaki kunieda. Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC, IEICE Trans. Fundamentals, Vol. E91-A, No. 7, pp. 1748 - 1756, July 2008.
• Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Fast and Accurate Singular Point Detection and Classfication on Quantized Orientation Field of Fingerprints, IEICE transaction on Information and System, accepted, July 2008.
• Tang Wei, 李 冬菊, 一色 剛, 國枝 博昭. Minutia Shape Indexing for Embedded Fingerprint Identification, IEICE transaction on Information and System, submitted, July 2008.
• Mohammad Zalfany Urfianto, Tsuyoshi Isshiki, Arif Ullah Khan, Dongju Li, Hiroaki Kunieda. A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development, IEICE transaction on Fundamentals, Vol. E91-A, No. 4, pp. 1185-1196, Apr. 2008.
• SUMEK WISAYATAKSIN, DONGJU LI, TSUYOSHI ISSHIKI, hiroaki kunieda. Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player, IEICE Trans. Fundamentals, Vol. E91-A, No. 4, pp. 1197-1205, Apr. 2008.
• Yiewn Wang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. A Novel Fingerprint SoC with Bit Serial FPGA Engine, Trans. of Information Processing Society of Japan, Vol. 46, No. 6, pp. 1366-1373, June 2005.
• Andy Surya Rikin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. A Fingerprint Matching using Minutia Ridge Shape for Low Cost Match-on-Card System, IEICE Trans. On Fundamental of Electronics, Communications and Computer Science, Vol. E88-A, No. 5, pp. 1305-1312, May 2005.
• Jinqing Qi, Dongju Li, Tsuyosyhi Isshiki, Hiroaki Kunieda. Binary Line-Pattern Algorithm for Embedded Fingerprint Authentication System, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, Vol. E87-A, No. 8, pp. 1879-1886, Aug. 2004.
• Jinqing Qi, Dongju Li, Tsuyosyhi Isshiki, Hiroaki Kunieda. Fast Fingerprint Classification based on Direction Pattern, IEICE Trans. On Fundamental of Electronics, Communications and Computer Science, Vol. E87-A, No. 8, pp. 1887-1892, Aug. 2004.
• Andy Surya Rikin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Small Memory Minutia Matching Method, IEEE ISPACS, Vol. 1, No. 1, Nov. 2003.
• Jinqing Qi, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Template-statistical based Fingerprint Classification, IEEE ISPACS, Vol. 1, No. 1, Nov. 2003.
• Yiwen Wang, Dongju Li, Tsuyosi Isshiki, Hiroaki Kunieda. A Fingerprint Authentication Programmable SoC Featuring Run-time Reconfigurable Interface, IEEE ISPACS, Vol. 1, No. 1, Nov. 2003.
• Gijun Idei, Hiroaki Kunieda. A False-Lock-Free Clock/Data recovery PLL for NRZ data Using Adaptive Phase Frequency Detector, IEEE, Trans. On CASI II, Analog and Digital Signal Processing, Vol. 11, No. November, 2003.
• Andy Surya Rikin, Wang Yi Wen, Taro Nakada, Li Dongju, Tsuyoshi Isshiki, Hiroaki Kunieda. Realization of Fingerprint Identification Module on DSP Board, Proceedings of 2002 IEEE Asia Pasific Conference on Circuit and System, Vol. 1, pp. 509-512, 2002.
• Trio Adiono, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Efficient Method for FaceRegion Quality Enhancement in Low Bit Rate Video Coding, Proceedings of 2002 IEEE Asia Pasific Conference on Circuit and System, Vol. I, pp. 549-553, 2002.
• T. Isshiki, A. Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Susila, D. Li, H. Kunieda. High Density Bit-Serial FPGA with LUT Embedding Shift Register Function, Proceedings of 2002 IEEE Asia Pasific Conference on Circuit and System, Vol. I, pp. 475-480, 2002.
• Trio Adiono, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. A New Methodology for Low Delay Real-time Videophone Software Architecture Design, Proceedings of 2002 IEEE Asia Pasific Conference on Circuit and System, Vol. II, pp. 269-273, 2002.
• Trio Adiono, Tsuyoshi Isshiki, Chawalit Honsawek, Kazuhito Ito, Dongju Li, Hiroaki Kunieda. New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec, IEICE Trans. Fundamentals, Vol. E85-A, No. 6, pp. 1396, 2002.
• Chawalit Honasawek, Kazuhito Ito, Tomohiko Ohtsuka, Trio Adiono, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. System-MSPA Design of H.263+Video Encoder/Decoder LSI for Videotelephony Applications, IEICE Trans. Fandamentals, Vol. E84-A, No. 11, pp. 2614-2622, 2001.
• Gijun Idei, Hiroaki Kunieda, Kazuyoshi Unno. A Clock Recovery PLL Applicable to Data Stream with Missing Pulses, IEICE Transaction, pp. 1663-1672, Aug. 2000.
• Abd Allah Mohamed, Dongju Li, Hiroaki Kunieda. Minutia Ridge Shape Algorithm for Fast on Line Fingerprint Identification System, IEEE Intelligent Signal Processings and Communication Systems 2000 (ISPACS 2000), 2000.
• Abd Allah Mohamed, Dongju Li, Hiroaki Kunieda. Minutia Ridge Shape Algorithm for Fast on Line Fingerprint Identification System, IEEE Intelligent Signal Processings and Communication Systems 2000 (ISPACS 2000), 2000.
• Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda. New FPGA Architecture for Bit Serial Pipeline Datapath, IEEE Transaction on Circuits and Systems II, Analog and Digital Signal Processing, No. 8, pp. 1663-1672, 2000.
• Gijun Idei, Hiroaki Kunieda, Kazuyoshi Unno. A Clock Recovery PLL Applicable to Data Stream with Missing Pulses, Proceedings of 2000 IEEE Asia-Pacific Conference on Circuits and Systems, 2000.
• Trio Adiono, Tsuyoshi Isshiki, Kazuhito Ito, Tomohiko Ohtsuka, Dongju Li, Chawalit Homsawek, Hiroaki Kunieda. Face Focus Coding Under H.263+ Video Coding Standard, Proceedings of 2000 IEEE Asia-Pacific Conference on Circuits and Systems, 2000.
• Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda. New FPGA Architecture for Bit Serial Pipeline Datapath, IEICE Transaction, No. 8, pp. 1663-1672, 2000.
• Tsuyoshi Isshiki, Makoto Ishikawa, Hiroaki Kunieda. Cost-Effective Shadowing Method Using ED-buffer on Adaptive Light Cube, The Visual Computer Journal, Vol. 16, No. 8, pp. 453-468, 2000.
• Dongju Li, Li Jiang, Hiroaki Kunieda. Design Optimization of VLSI Array Processor Architecture for Window Image Processing, The Institute of Electronics, Information and Communication Engineers Transactions(IEICE TRANS) on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on Digital Signal Processing, Vol. E82-A, No. 8, pp. 1475-1484, Aug. 1999.
• Dongju Li, Li Jiang, Tsuyoshi Isshiki, hiroaki kunieda. New VLSI Array Processor Design for Image Window Operations, IEEE Transactions, Vol. 46, No. 5, pp. 635-639, May 1999.
• Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda. Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm, IEICE TRANS. Fundamentals, Vol. E81-A, No. 8, pp. 1667-1675, Aug. 1998.
• Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda. New FPGA Architecture for Bit-Serial Pipeline Datapath, Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, Vol. 1, No. 1, 1998.
• Dongju Li, Li Jiang, Tsuyoshi Isshiki, Hiroaki Kunieda. New VLSI Array Processor Design for Image Window Operations, IEEE, Vol. 1, No. 1, pp. 1-1, 1998.
• Tsuyoshi Isshiki, Wayne Wei-Ming Dai, Hiroaki Kunieda. Routability Analysis of Bit-Serial Pipeline Datapaths, EICE TRANS, Vol. .E80-A, No. 8, Oct. 1997.
• Li Jiang, Kazuhito ITO, Hiroaki Kunieda. Bits Truncation Adaptive Pyramid Algorithm for Motion Estimation of MPEG2, IEICE TRANS, Vol. E80-A, No. 8, pp. pp1438-pp1445, Aug. 1997.
• Kyung-Sik Jang, Hiroaki Kunieda. A New Approach for Datapath Synthesis of Application Specific Instruction Processor, IEICE TRANS, Vol. E80-A, No. 8, pp. pp1478-pp1488,, Aug. 1997.
• Kyung-Sik Jang, Tsuyoshi Isshiki, Hiroaki Kunieda. Instruction Sequence Based Synthesis for Application Specific Micro-Architecture, IEICE TRANS, Vol. E80-A, No. 6, June 1997.
• Joon Tae Kim, Yong Hoon Lee, Tsuyoshi Isshiki, Hiroaki Kunieda. Scalable VLSI Architectures for Lattice Structure Based Discrete Wavelet Transform, IEEE Trans, Vol. 1, No. 1, pp. 1-1, Feb. 1997.
• Dongju Li, Hiroaki Kunieda. Automatic Synthesis of a Serial Input Multiprocessor Array, IEICE TRANS, Vol. E79-A, No. 12, Dec. 1996.
• Dongju Li, Hiroaki Kunieda. Memory Sharing Processor Array(MSPA) Architecture, IEICE Trans. Fundamentals, Vol. E79-A, No. 12, pp. 1-1, Dec. 1996.
• A.F. Mas'ud, T. Ohtsuka, Hiroaki Kunieda. Translation of Specifications in Hierarchical Analog LSI Design, IEEE, Vol. 1, No. 1, pp. 735-738, May 1996.
• Dongju Li, Hiroaki Kunieda. ASIC Array Processor Design for Regular Algorithm, Proceedings of RC-TCCAS, Vol. 1, No. 1, 1996.
• Takashi Shimizu, Hiroaki KUNIEDA. A Cost-Effective Network for Very Large ATM Cross-Connects --- The Delta Network with Expanded Middle Stages---, IEICE Trans, E77-B, No. 11, pp. 429-1436, Nov. 1994.
• Zhaochen Huang, Yoshinori Takeuchi, Hiroaki KUNIEDA. Distributed Load Balancing Schemes for Parallel Video Encoding System, IEICE Trans, Vol. E77-A, No. 5, pp. 923-930, May 1994.
• Yoshinori TAKEUCHI, Zhao-Chen HUANG, Masatomo SAEKI, Hiroaki KUNIEDA. RHINE: Reconfigurable Multiprocessor System for Video CODEC, IEICE Trans, Vol. E76-A, No. 6, pp. 947-956, June 1993.
• Tomohiko OHTSUKA, Nobuyuki KUROSAWA, Hiroaki KUNIEDA. The Improvement in Performance-Driven Analog LSI Layout System LIBRA, IEICE Trans, Vol. E76-A,, No. 10, pp. 1626-1635, June 1993.
• Yoshinori TAKEUCHI, Hiroaki KUNIEDA. Space Partitioning Image Processing Technique for Parallel Recursive Half Toning, IEICE Trans, Vol. E76-A, No. 4, pp. 603-612, Apr. 1993.
• Tsuyoshi ISSHIKI, Yoshinori TAKEUCHI, Hiroaki KUNIEDA. Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Graph, IEICE Trans, Vol. E76-A, No. 3, pp. 337-348, Mar. 1993.
• Kazuhito ITO, Kesami HAGIWARA, Takashi Shimizu, Hiroaki KUNIEDA. Modulation and Processor Placement for DSP Neo-Systolic Array, IEICE Trans, Vol. E76-A, No.3, No. 3, pp. 349-361, Mar. 1993.
• Norichika KUMAMOTO, Keiji Aoki, Hiroaki KUNIEDA. VIRGO: Hierarchical DSP Code Generator Based on Vectorized Signal Flow Graph Description, IEICE Trans, Vol. E75-A, No. 8, pp. 1004-1034, Aug. 1992.
• Tomohiko OHTSUKA, Hiroaki KUNIEDA, Mineo KANEKO. LIBRA: Automatic Performance-Driven Layout for Analog LSIs, IEICE Trans, Vol. E75-C, No. 3, pp. 312-320, Mar. 1992.
• Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, Mineo KANEKO. Two-Dimensional Quadrilateral Recursive Digital Filters with Parallel Structure -Synthesis and Parallel Processing, IEICE Trans, Vol. E75-A,, No. 3, pp. 352-361, Mar. 1992.
• Mineo KANEKO, Kimihiko KAZUI, Hiroaki KUNIEDA. An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks, IEICE Trans, Vol. 1, No. 1, pp. 1-1, Feb. 1992.
• K.Itoh, H.Kunieda. VLSI System Compiler for Digital Signal Processing: Modularization and Synchronization,, IEEE, Vol. 38, No. 4, pp. 423-433, Apr. 1991.
• Y.Takeuch, H.Kunieda. Two Dimensional Space Partitioning Recursive Filtering Algorithm on Rectangular Processor Array, IEICE Trans, Vol. 1, No. 1, pp. 1-1, Feb. 1991.
• M.Fujita, H.Kunieda. A Hardware Implementation of Fast Scaling Algorithm in Residue Number DSP Systems, IEICE Trans, Vol. 1, No. 1, pp. 1-1, 1988.
• H.Kunieda, K.Itoh. A 2D-FFT Algorithm on Mesh Connected Multiprocessor Systems, IEICE Trans, Vol. 71-A, No. 7, pp. 1424-1431, 1988.
• H.Kunieda, M.Watabiki. Yield Estimation for Analog Integrated Circuits, IEICE Trans, Vol. 1, No. 1, pp. 1-1, 1982.
• H.Kunieda. Sensitivity Analysis of Switched Capacitor Networks by using Adjoint Networks, IEICE Trans, Vol. 1, No. 1, pp. 1-1, 1982.
• M.Kaneko, H.Kunieda, M.Onoda. Topological Property for Switched Capacitor Networks, IEICE Trans, Vol. 1, No. 1, pp. 1-1, 1982.
• H.Kunieda, M. Kaneko. Equivalent Representation of Switched Capacitor Networks and its Applications, IEICE Trans, Vol. 1, No. 1, pp. 1-1, 1982.
• H.Kunieda. Simplified Equivalent Representations for Multicoupled Lines and their Application to Filter Design, IEEE, Vol. 1, No. 1, pp. 1-1, 1980.
• H.Kunieda. Equivalent Representation of Disspative Multiwire Lines by using Lumped Element, IEICE, Vol. 1, No. 1, pp. 1-1, 1980.
• H.Kunieda, M.Onoda. Equivalent Representation of Multiwire Transmission-Line Transformers and its Applications to the Design of Hybrid Networks, IEICE, Vol. 1, No. 1, pp. 1-1, 1980.
• H.Kunieda, M.Onoda. Equivalent Representation of Multiwire Transmission-Line Transformers and its Applications to the Design of Hybrid Networks, IEEE, Vol. 1, No. 1, pp. 1-1, 1980.
• H.Kunieda, M.Onoda. Lumped Equivalent Representation of Nondisspative Multiwire Lines in an Inhomogeneous Medium, IEICE, Vol. 1, No. 1, pp. 1-1, 1978.
• M.Onoda, H.Kunieda. Lumped Element Equivalent Representation of Distributed Networks and its Applications, IEICE, Vol. 1, No. 1, pp. 1-1, 1977.
• H.Kunieda, H.Sakurai, M.Onoda. Equivalent Circuit Representation of Multiwire Transmission-Line Transformers and its Applications to Design of Hybrid Networks, IEICE, Vol. 1, No. 1, pp. 1-1, 1977.
• H.Kunieda, M.Onoda. On State Space Equation of Linear Active Networks Based on the Nullator-Norator Models, IEICE, Vol. 1, No. 1, pp. 1-1, 1974.

著書

• 國枝 博昭, 伊藤 和人. コンピュータアーキテクチャ, 科学技術出版, Sept. 1999.
• 國枝 博昭. 集積回路設計入門, コロナ社, July 1997.
• Tsuyoshi Isshiki, Wayne Wei-Ming Dai, Hiroaki Kunieda. Bit-Serial Pipeline Synthesis and Layout for Large-Scale Configurable Systems, 1997 Asia South Pacific Design Automation Conference, Vol. 1, No. 1, pp. 441-446, Jan. 1997.
• Kazuhito Ito, Tadashi Iwata, Hiroaki Kunieda. An Optimal Scheduling Method for Parallel Processing System of Array Architecture, Proceedings of 1997 Asia South Pacific Design Automation Conference, pp. 447-454, Jan. 1997.
• Kyung-Sik Jang, Hiroaki Kunieda. Topological Transformation for Application Specific Instruction-set Processor Datapath Synthesis, Int. Tech. Conf. on Circuit and Systems, Computer, Communication, Vol. 1, No. 1, 1996.
• 國枝 博昭. なっとくする電気回路, 講談社, July 1995.
• Yoshinori Takeuchi, Tsuyoshi Isshiki, Hiroaki Kunieda. Parallel Algorithm for Recursive Linear Filtering on Transputers, IOS Press, 1992.
• M. Takebe, A. Iwata, Takahashi, H.Kunieda. Switched Capacitor Circuits, 1985.
• H.Kunieda, M. Onoda. Exercise of Circuit Analysis, Shokhodo, 1981.

国際会議発表 (査読有り)

• Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. An Efficient Embedded Processor for Object Detection Using ASIP Methodology, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2016.
• Nabilah Shabrina, Tsuyoshi Isshiki, Hiroaki Kunieda. Fingerprint Authentication on Touch Sensor using Phase-Only Correlation Method, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2016.
• Shanlin Xiao, Dongju Li, Hiroaki Kunieda, Tsuyoshi Isshiki. Design of an Efficient ASIP-Based Processor for Object Detection Using AdaBoost Algorithm, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2016.
• Ikumi Endo, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. A Design Method for Real-Time Image Denoising Circuit using High-Level Synthesis, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2016.
• Supawan Kumpituck, Dongju Li, Hiroaki Kunieda, Tsuyoshi Isshiki. Fingerprint spoof detection using wavelet based local binary pattern, Graphic and Image Processing (ICGIP), Feb. 2016.
• Dongju Li, Hiroaki Kunieda, Supawan Kumpituck, Tsuyoshi Isshiki. Online Detection of Spoof Fingers for Smartphone-Based Applications, IEEE 7th International Symposium on Cyberspace Safety and Security (CSS), Aug. 2015.
• Pipat Methavanitpong, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Branch Bitstream: Machine Instruction-level System Tracing, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2015.
• Kensuke Fujiya, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. C-Based RTL Design Method for Circuit Switched Network on Chips, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2015.
• Masao Yamazaki, Hiroaki Kunieda, Dongju Li, Tsuyoshi Isshiki. SIFT-based Algorithm for Fingerprint authentication on smartphone, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2015.
• Tsuyoshi Isshiki, Koshiro Date, Daisuke Kugimiya, Dongju Li, Hiroaki Kunieda. C-Based RTL Design Framework for Processor and Hardware-IP Synthesis, Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Mar. 2015.
• Surachai Thongkaew, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension With Hybrid Execution, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2014.
• Amr Fathy, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Custom Instruction Search for Application Specific Instruction-Set Processor using Guided Simulated Annealing, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2014.
• Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Guanyu Zhu. Distributed Synchronization for Message-Passing Based Embedded Multiprocessors, IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), June 2014.
• Amr Yehia, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Custom Instruction Synthesis Framework for Application Specific Instruction-Set Processor with HW, Jan. 2014.
• Yang Li, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Processor Elements Allocation Exploration for 2D Mesh Network-on-Chip Architecture, Jan. 2014.
• Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Efficient Synchronization for Message-passing based Embedded Multiprocessors, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2014.
• Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. ASIP Design and FPGA Implementation of Fingerprint Authentication Application, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2014.
• Yang Li, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda. Design Space Exploration for Network-on-Chip Architecture Optimization, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2013.
• Surachai Thongkaew, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda. Improving Android Performance Using Dalvik Hardware Extension Architecture (TCT-Dalvik Processor), International Conference on Information and Communication Technology for Embedded Systems, Jan. 2013.
• Mochamad Asri, Hsuan Chun Liao, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda. A Reconfigurable ASIP-Based Approach for High Performance Image Signal Processing, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2012.
• TSUYOSHI ISSHIKI, Hao Xiao, Hsuan Chun Liao, DONGJU LI, hiroaki kunieda. Application-Specific Instruction-Set Processor Design Methodology for Wireless Image Transmission Systems, International SoC Design Conference, Nov. 2012.
• Hsuan Chun Liao, Mochamad Asri, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda. A Reconfigurable High Performance ASIP Engine for Image Signal Processing, IEEE 26th International Parallel and Distributed Processing Symposium, May 2012.
• Mohamad Asri, Hsuan Chun Liao, TSUYOSHI ISSHIKI, hiroaki kunieda. Bridging the Gap between ASIC and GPP : A High-Performance and C-Programmable ASIP for Image Processing, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2012.
• Hao Ni, DONGJU LI, TSUYOSHI ISSHIKI, hiroaki kunieda. Robust Multiple Minutiae Partitions for Fingerprint Authentication, The 2012 IEEE International Symposium on Biometrics and Security Technologies (ISBAST’12), Mar. 2012.
• Supawan Kumpituck, DONGJU LI, TSUYOSHI ISSHIKI, hiroaki kunieda. A Study of Fingerprint Image Enhancement by Example-Based Super-Resolution, International Conference on Information Communication Technology for Embedded Systems, International Conference on Information and Communication Technology for Embedded Systems, Mar. 2012.
• Hao NI, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA. Robust Multiple Minutiae Partitions for Fingerprint Authentication, The 2012 IEEE International Symposium on Biometrics and Security Technologies (ISBAST’12), The 2012 IEEE International Symposium on Biometrics and Security Technologies (ISBAST’12), Mar. 2012.  公式リンク  
  
• Hao Xiao, TSUYOSHI ISSHIKI, hiroaki kunieda. Hybrid Shared-memory andMessage-passing Multiprocessor System-on-Chip for UWB MAC, International Conference on Consumer Electronics (ICCE), International Conference on Consumer Electronics (ICCE), Jan. 2012.
• Syunsuke Sato, Hsuan－Chun Liao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Design of High Performance Application－Specific Image Processors for Multiprocessor SoCs, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2011.
• Junpei Ikeno, Farhan Nawaz, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. Design of Application Specific Instruction－set Processor for Deblocking Filter Module of H.264, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2011.
• Arif Ullah Khan, Ken Takahashi, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Hardware Accelerator Integration methodology for Application Specific Multiprocessor System on Chip Using Shares Data Memory, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2011.
• YuKun Liu, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. A Novel Similarity Measurement for Minutiae-based Fingerprint Verification, Biometrics: Theory Applications and Systems (BTAS), 2010 Fourth IEEE International Conference, Biometrics: Theory Applications and Systems (BTAS), 2010 Fourth IEEE International Conference, Sept. 2010.
• Hao Ni, DONGJU LI, TSUYOSHI ISSHIKI, Hiroaki Kunieda. Unique Fingerprint Image Generation Algorithm for One Line Swipe Sensors, International Conference on Information and Communication Technology for Embedded System(ICICTES 2010), Proceedings of International Conference on Information and Communication Technology for Embedded System(ICICTES 2010), Jan. 2010.
• Wei Li, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. A Rule Based Repair for Fingerprint Minutia Extraction, International Conference on Information and Communication Technology 2010, Jan. 2010.
• Sang Woo Sin, Ru Zhou, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Online Fingerprint Template Updating in Mobile Application, International Conference on Information and Communication Technology 2010, Jan. 2010.
• Munenori Nakayama, TSUYOSHI ISSHIKI, Dongju LI, Hiroaki kunieda. Multiprocessor System-On-Chip Design Methodology Using Model-Based Tightly-Coupled Thread Model, International Conference on Information and Communication Technology for Embedded System(ICICTES 2010), Proceedings of International Conference on Information and Communication Technology for Embedded System(ICICTES 2010), Jan. 2010.
• Ru Zhou, SangWoo Sin, Dongju LI, TSUYOSHI ISSHIKI, Hiroaki Kunieda. Fast Search for Fingerprint Matching in Embedded System, International Conference on Information and Communication Technology for Embedded System(ICICTES 2010), Proceedings of International Conference on Information and Communication Technology for Embedded System(ICICTES 2010), Jan. 2010.
• Jinqing Qi, DONGJU LI, TSUYOSHI ISSHIKI, Hiroaki Kunieda. Architecture of Dynamic Reconfigurable Neural Networks Based ib Network-on-Chip, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2010.
• Wei Tang, DONGJU LI, TSUYOSHI ISSHIKI, Hiroaki Kunieda. Fingerprint Reference Point Extraction in Small Size Sensor Images, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2010.
• YuKun Liu, DONGJU LI, TSUYOSHI ISSHIKI, Hiroaki Kunieda. A Novel Fingerprint Orientation Field Estimation Method, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2010.
• Hsuan-Chun Liao, Syunsuke Sato, Hiroshi Koami, TSUYOSHI ISSHIKI, DONGJU LI, Hiroaki Kunieda. High-Speed Video Processing System-On-Chip Architecture Exploration, International Conference on Information and Communication Technology for Embedded Systems, Jan. 2010.
• TSUYOSHI ISSHIKI, hiroaki kunieda, DONGJU LI. Trace-Driven Workload Simulation Method for Multiprocessor System-On-Chips, Design Automation Conference, June 2008.
• Sumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. H.264/AVC Decoder SoC Towards the Low Cost Mobile Video Player, IEEE SOC Conference, Proceedings of IEEE SOC Conference, Sept. 2007.
• Li Dongju, Hiroaki Kunieda. Programmable Design for Memory Sharing Processor Array (MSPA), Proceedings of IEEE 1997 International Symposium on Circuit and Systems, Vol. 1, No. 1, June 1997.

国内会議発表 (査読有り)

• T. Pipatpongsa, T. Moriizumi, T. Kitahara, T. Shimura, H. Kunieda, A. Nishihara. Educational drive of Tokyo Tech toward human resources development in Thailand, the 1st Thailand-Japan International Academic Conference, Proceedings of the 1st Thailand-Japan International Academic Conference (1st TJIA 2008), 在日タイ留学生協会, pp. 175-176, Nov. 2008.

国際会議発表 (査読なし・不明)

• Andy Surya Rikin, Yiwen Wang, Taro Nakada, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. Realization of Fingerprint Identification Module on DSP Board, Proc. Of 2002 IEEE Asian Pacific Conference on Circuit and System, pp. 509-512, 2002.
• Gijun Idei, Hiroaki Kunieda, Kazuyoshi Unno. A Clock Recovery PLL Applicable to Data Stream with Missing Pulses, Proceedings of APCCAS 2000, Vol. 1, No. 1, pp. 509, Dec. 2000.
• Abd Allah Mohamed Mostafa, Dongju Li, Hiroaki Kunieda. Minutia Ridge Shape Algorithm For Fast On Line Fingerprint Identification System, ISPACS 2000, Vol. 1, No. 1, Nov. 2000.
• hiroaki kunieda. Efficient Anti-Aliasing Algorithm for Computer Generated Images, Internatinal Symposium on Intelligent Signal Processing and Communication Systems, Tsuyoshi Isshiki and Hiroaki Kunieda,, Vol. 1, No. 1, Dec. 1999.
• Dongju Li, Trio Adiono, Chawalit Honsawek, Hiroaki Kunieda. Multimedia LSI Design Based on Window-MSPA Architecture, Internatinal Symposium on Intelligent Signal Processing and Communication Systems, Vol. 1, No. 1, Dec. 1999.
• Dongju Li, Trio Adiono, Chawalit Honsawek, Hiroaki Kunieda. Multimedia LSI Design Based on Window-MSPA Architecture, Internatinal Symposium on Intelligent Signal Processing and Communication Systems, Vol. 1, No. 1, Dec. 1999.
• Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda. A New High Logic Density FPGA for Bit-Serial Pipeline Datapath, The 1998 IEEE Asia-Pacific Conference on Cirucuits and Sytems, Vol. 1, No. 1, Nov. 1998.
• Akihiro Oue, Tsuyoshi Isshiki, Hiroaki Kunieda. MPEG Video Encoder Based on Run-Time Reconfigurable Architecture, The 3rd International Conference on ASIC, Vol. 1, No. 1, Oct. 1998.
• Dongju Li, Li Jiang, Tsuyoshi Isshiki, Hiroaki Kunieda. Array Architecture and Design for Image Window Operation Processing ASICs, Proceedings of IEEE 1998 International Symposium on Circuits and Systems, Vol. 1, No. 1, June 1998.
• Dongju Li, Li Jiang, Tsuyoshi Isshiki, Hiroaki Kunieda. Towards One Chip HDTV MPEG2 Encoder LSI, Towards One Chip HDTV MPEG2 Encoder LSI, pp. 173-176, May 1998.
• Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda. A new FPGA Architecture for High-Performance Bit-Serial Pipeline Datapath, Proceedings of Sixth ACM International Symposium on Field-Programmable Gate Arrays, Vol. 1, No. 1, Feb. 1998.
• Kazuhito Ito, Takanobu Shimizugashira, Hiroaki Kunieda. High Speed Bit-Serial Parallel Processing on Array Architecture, Proceedings of 1997 Asia South Pacific Design Automation Conference, Vol. 1, No. 1, pp. 667-668, Jan. 1997.
• Dongju Li, Hiroaki Kunieda. New Array Processor Architecture for MPEG2 Motion Estimation, Proceedings of 7th International Symposium on IC Technology, Systems & Applicatons, pp. 632-635, 1997.
• Dongju Li, Hiroaki Kunieda. ASIC Array Processor Design for Regular Algorithm, Proceedings of RC-TCCAS, Thailand, Vol. 1, No. 1, pp. 1-1, July 1996.
• Dongju Li, Hiroaki Kunieda. Memory Sharing Processor Array (MSPA) and its Design Methodology, 1996 Int. Conf. on Computing and Information, Vol. 1, No. 1, pp. 1-1, June 1996.
• Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito. Automatic Desing for Bit-serial MSPA Architecture, 1995 Asia South Pacific Design Automation Conference, Vol. 1, No. 1, pp. 1-1, 1995.
• Hiroaki Kunieda, Kesami Hagiwara. Effective Processor Array Architecture with Shared Memory, 1994 Asia-Pacific Conference on Circuits and Systems, Vol. 1, No. 1, pp. 1-10, 1994.
• Tomohiko Ohstuka, Phua Boon Chung, Hiroaki Kunieda. MOS Analog LSI Performance-Driven Layout with Device Shape Optimization, 1994 Joint Technical conference on Circuits/Systems, Vol. 1, No. 1, 1994.
• Masatomo SAEKI, Yoshinori TAKEUCHI, Hiroaki KUNIEDA. High Speed Iterated Transformation TheoryBased Coding using Wavelet Transformation, ISPACS94, Vol. 1, No. 1, pp. 1-1, 1994.
• Yoshinori TAKEUCHI, Kenji SHIBATA, Hiroaki KUNIEDA. Codesign Methodology on Programmable Hardware and Software System, 1994 Asia-Pacific Conference on Circuits and Systems, Vol. 1, No. 1, pp. 1-1, 1994.
• Yoshinori TAKEUCHI, Tatsuyuki NEGISHI, Hiroaki KUNIEDA. A Parallel Image Compression Algorithm Using Space Partitioning Wavelet Transform, 1993 Joint Technical conference on Circuits/Systems, Vol. 1, No. 1, pp. 622-627, July 1993.
• Tomohiko Ohtsuka, Nobuyuki KUROSAWA, Hiroaki KUNIEDA. Optimization of Device Heat and Wire Parastics in Performance Driven Analog Layout System LIBRA, Proceedings of 1992 Asia-Pacific Conference on Circuits and Systems, Vol. 1, No. 1, pp. 1-1, Dec. 1992.
• Kazuhito ITO, Kesami Hagiwara, Hiroaki KUNIEDA. Neo-Systolic Array: A Hardware Model for VLSI System Compiler VEGA, Proceedings of 1992 Asia-Pacific Conference on Circuits and Systems, Vol. 1, No. 1, pp. 1, Dec. 1992.
• Tsuyoshi Isshiki, Yoshinori TAKEUCHI, Hiroaki KUNIEDA. Systematic Architecture Design for Highly Parallel Image Processing Algorithms, Proceedings of 35th Midwest Symposium on Circuits and Systems, Vol. 1, No. 1, pp. 1-1, Aug. 1992.
• Yoshinori Takeuchi, Zhao-Chen HUANG, Masatomo SAEKI, Hiroaki Kunieda. Reconfigurable Multiprocessor System RHINE for Moving Picture Codec, 1992 Joint Technical conference on Circuits/Systems, computers and Communications, Vol. 1, No. 1, pp. 45-50, July 1992.
• Hiroaki KUNIEDA, Kazuhito ITO, Norichika KUMAMOTO. Topics on VLSI Signal Processing, Vol. 1, No. 1, pp. 1-10, 1992.
• K.Itoh, T.Shimizu, H.Kunieda. VLSI System Compiler for Digital Signal Processing: Extended Modularization and Placement, IEEE, Vol. 1, No. 1, pp. 1-1, 1991.
• Y.Takeuchi, H.Kunieda. Parallel Implementation for Digital Half Toning, Joint Technical Conference on Circuits/Systems, Computers and Comunications, Vol. 1, No. 1, pp. 1-1, 1991.
• H.Kunieda. Vectorized Signal Flow Graph Representation and Hierarchical Scheduling for Digital Signal Processing, Asilomar Conference on Circuits, Vol. 1, No. 1, pp. 1-1, 1990.
• H.Kunieda. Static Parallel Multiprocessor Scheduling for Digital Signal Processing Based on Vectorized Signal Flow Graph Representation, IEICE, Vol. 1, No. 1, pp. 1-1, 1990.
• Y.Takeuchi, H.Kunieda. Two Dimensional Space Segmentation Recursive Filtering Algorithm on Rectangular Processor Array, IEEE, Vol. 1, No. 1, pp. 1-1, 1990.
• K.Itoh, H.Kunieda. The Modularization and Synchronization of Digital Signal Processing Algorithms, Proceedings of International Conference on Circuits and Systems, Vol. 1, No. 1, pp. 1-1, 1989.
• H.Kunieda, S.Toyoshima. Parallel Processor Scheduling for Digital Signal Processing, IEEE, Vol. 1, No. 1, pp. 1-1, 1989.
• H.Kunieda, A.Oshimo. State Space Approach to the Design for Low Passband Sensitivity Switched Capacitor Filters, IEEE, Vol. 1, No. 1, pp. 1-1, 1984.
• H.Kunieda. Effects on Finite Gain-Bandwidth Products of OP Amps on Switched-Capacitor Networks, IEEE, Vol. 1, No. 1, pp. 1-1, 1982.
• H.Kunieda. General Design Method for Distributed Coupled-Line Bandpass Filters, IEEE, Vol. 1, No. 1, pp. 1-1, 1979.
• M.Onoda, H.Kunieda. Lumped-Element Equivalent Representation of Transmission-Line Networks by Half-Angle Richard's Variable, IEEE, Vol. 1, No. 1, pp. 1-1, 1978.
• Ilse Noerbambang, Hiroaki Kunieda. Direct Tuning Scheme in Continuous-Time Biquad Filter with Operational Transconductance Amplifiers, Proceedings of 7th International Symposium on IC Technology, Systems & Applicatons, pp. 636-639, Sept. 1977.

国内会議発表 (査読なし・不明)

• J. Ceng, J. Castrillon, W. Sheng, H. Scharwachter, R. Leupers, G. Ascheid, H. Meyr, T. Isshiki, H. Kunieda. MAPS: An Integrated Framework for MPSoC Application Parallelization, Proceedings of 45th Design Automation Conference (2008), June 2008.
• Arif Ullah Khan, Mohammad Zalfany Urfianto, Tsuyoshi Isshiki, DongJu Li, Hiroaki Kunieda. Embedded Software Development Flow and Verification for a Heterogeneous MPSoC Based on Tightly Coupled Thread Model, Embedded Systems Symposium 2007, Embedded Systems Symposium 2007, Oct. 2007.

その他の論文・著書など

• 杉野暢彦, 一色 剛, 西原明法, 國枝博昭. バンコクだより 東工大から世界へ ～タイ国との連携大学院TAIST-Tokyo Techの取り組み～, Fundamentals Review, 電子情報通信学会, Vol. 12, No. 4, pp. 102-105, Apr. 2009.

特許など

• 國枝博昭, 李冬菊. 機密生体サーバー認証. 特許. 登録. 国立大学法人東京工業大学, 株式会社シービーエージャパン. 2013/09/26. 特願2013-199346. 2015/04/09. 特開2015-064818. 特許第6222692号. 2017/10/13 2017.
• 一色剛, 國枝博昭, 小林　直人. 実行時間推定方法、実行時間推定プログラムおよび実行時間推定装置. 特許. 登録. 国立大学法人東京工業大学. 2009/06/23. 特願2010-519006. 2011/12/22. 特開（再表）2010/001766. 特許第5403760号. 2013/11/08 2013.
• 一色剛, 國枝博昭. プログラム処理装置、プログラム処理方法、並列処理プログラム用コンパイラおよび並列処理プログラム用コンパイラを格納した記録媒体. 特許. 登録. 国立大学法人東京工業大学. 2006/01/17. 特願2006-008779. 2007/08/02. 特開2007-193423. 特許第4830108号. 2011/09/30 2011.
• 一色剛, 國枝博昭. プログラム処理装置、並列処理プログラム、プログラム処理方法、並列処理コンパイラ、並列処理コンパイラを格納した記録媒体およびマルチプロセッサシステム. 特許. 登録. 国立大学法人東京工業大学. 2006/01/17. 特願2006-008870. 2007/08/02. 特開2007-193430. 特許第4923240号. 2012/02/17 2012.

学位論文

• 分布定数回路網の集中素子等価表現とその応用に関する研究,  本文,  工学博士,  東京工業大学,  1978/03/26,   

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