"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","Two-layer Bottleneck Channel Track Assignment for Analog VLSI",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 17",,"pp. 67-76",2024,June
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP",,"Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024)",,,,"pp. 50-55",2024,Mar.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi TAKAHASHI,モロンゴ マチュー,Makoto Minami,西岡克也","Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2023-103)",,"Vol. 123","No. 390","pp. 24-29",2024,Feb.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Molongo Mathieu,Makoto Minami,Katsuya Nishioka","Three-layer Bottleneck Channel Track Assignment by ILP",,"Proc. DA Symposium 2023, IPSJ Symposium Series",,,,"pp. 199-206",2023,Aug.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Molongo Mathieu,Makoto Minami,Katsuya Nishioka","Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2022-101)",,"Vol. 122","No. 402","pp. 149-154",2023,Mar.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Yukichi Todoroki,Makoto Minami","Bottleneck Channel Routing to Reduce the Area of Analog VLSI",,"Proc. the 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2022)",,,,"pp. 26-31",2022,Oct.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Yukichi Todoroki,Makoto Minami","Bottleneck Channel Routing to Reduce the Area of Analog VLSI","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2021-77)",,"Vol. 121","No. 412","pp. 7-12",2022,Mar.