"Shimpei Sato,Hiroshi Nakatsuka,Atsushi Takahashi","Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection",,"Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016)",,,,"pp. 60-65",2016,Oct.
"中塚裕志,高橋篤司","動的タイミングエラー検出を用いた可変レイテンシ化による一般同期式回路の高性能化","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2015-140)",,"Vol. 115","No. 465","pp. 167-172",2016,Mar.
"Shinya Takamaeda-Yamazaki,HIroshi Nakatsuka,Yuichiro Tanaka,Kenji Kise","Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Detapaths for FPGAs",,"IEICE Transagion on Informaion and Systems",,"Vol. E-98-D","No. 12","pp. 2150-2158",2015,Dec.
"Hiroshi Nakatsuka,Yuichiro Tanaka,Thiem Van Chu,Shinya Takamaeda-Yamazaki,Kenji Kise","Ultrasmall: The Smallest MIPS Soft Processor","24th International conference on Field Programmable Logic and Applications(FPL2014)",,,,,"pp. 1-4",2014,Sept.
"Hiroshi Nakatsuka,Kenji Kise","FPGA Area Reduction with Uncommon Usage of Reset Signals","情報処理学会第76回全国大会",,,,,,2014,Mar.
"中塚 裕志,池田 貴一,吉瀬 謙二","FPGAの特徴に着目した動作周波数の向上による汎用プロセッサの高速化",,"情報処理学会研究報告2014-ARC-208",,,"No. 5","pp. 1-2",2014,Jan.