"Takashi Sato,Hiroyuki Ueyama,Noriaki Nakayama,Kazuya Masu","Accurate array-based measurement for subthreshold-current of MOS",,"IEEE Journal of Solid-State Circuits","IEEE Journal of Solid-State Circuits","Vol. 44","No. 11","pp. 2977-2986",2009,Nov.
"Michihiro Shintani,Takumi Uezono,Tomoyuki Takahashi,Hiroyuki Ueyama,Takashi Sato,Kasumi Hatayama,Takashi Aikyo,Kazuya Masu","An Adaptive Test for Parametric Faults Based on Statistical Timing Information","IEEE Asian Test Symposium","IEEE Asian Test Symposium","IEEE Asian Test Symposium",,,"pp. 151-156",2009,Nov.
"新谷 道広,高橋 知之,植山 寛之,上薗 巧,佐藤 高史,畠山 一実,相京 隆,益 一哉","統計的タイミング情報に基づく適応型テスト",,"2009 年 電子情報通信学会総合大会",,,,"  D-10-16",2009,Mar.
"上薗 巧,高橋 知之,植山 寛之,新谷 道広,佐藤 高史,益 一哉","適応型テストにおけるクリティカルパスのクラスタリング手法","2009 年 電子情報通信学会総合大会","2009 年 電子情報通信学会総合大会","電子情報通信学会",,"  D-10-17","p. 160",2009,Mar.
"Takashi Sato,Hiroyuki Ueyama,Noriaki Nakayama,Kazuya Masu","A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation","IEEE Asian solid-state circuit conference (ASSCC)","IEEE Asian solid-state circuit conference (ASSCC)","IEEE Asian solid-state circuit conference (ASSCC)",,,"pp. 389-392",2008,Nov.
"Noriaki Nakayama,Takashi Sato,Hiroyuki Ueyama,Kazuya Masu","An efficient extraction of random and systematic gate-length variation through poly-Si resistor measurement","Workshop on test structure design for variability characterization","Workshop on test structure design for variability characterization",,,,,2008,Nov.
"高橋知之,植山寛之,萩原 汐,佐藤高史,益 一哉","論理セル遅延の電圧・プロセスばらつき感度の検討","電子情報通信学会ソサイエティ大会","電子情報通信学会ソサイエティ大会",,,"  A-3-2","pp. 52",2008,Sept.
"植山寛之,佐藤高史,中山範明,益 一哉","抵抗測定法によるトランジスタアレイ回路の測定時間短縮化","電子情報通信学会ソサイエティ大会","電子情報通信学会ソサイエティ大会",,,"  C-12-41","pp. 110",2008,Sept.
"植山寛之,佐藤高史,中山範明,益 一哉","リーク電流測定用トランジスタアレイ回路の測定","電子情報通信学会 総合大会","電子情報通信学会 総合大会",,,"  A-3-14","pp. 89",2008,Mar.
"植山寛之,佐藤高史,中山範明,益 一哉","リーク電流測定用トランジスタアレイ回路の測定","電子情報通信学会 総合大会","電子情報通信学会 総合大会",,,,"pp. A-3-14",2008,Mar.
"Takashi Sato,Hiroyuki Ueyama,Noriaki Nakayama,Kazuya Masu","Determination of optimal polynomial regression function to decompose on-die systematic and random variations","ACM/IEEE Asia South Pacific Design Automation Conference (ASPDAC)","ACM/IEEE Asia South Pacific Design Automation Conference (ASPDAC)",,,,"pp. 518-523",2008,Jan.
"植山寛之,佐藤高史,中山範明,益 一哉","閾値電圧の大域ばらつきが回路遅延ばらつきに与える影響","STARCシンポジウム",,,,,,2007,Sept.
"植山寛之,佐藤高史,中山範明,益 一哉","大域ばらつきの近似次数が回路遅延ばらつきに与える影響","電子情報通信学会ソサイエティ大会",,,,"No. A-1-8","pp. 8",2007,Sept.