"–‘‘]–μ ’q—η,‹g£ Œͺ“ρ","FPGAƒAƒNƒZƒ‰ƒŒ[ƒVƒ‡ƒ“‚π‰Β”\‚Ι‚·‚ιƒXƒgƒŠ[ƒ~ƒ“ƒOƒtƒŒ[ƒ€ƒ[ƒN‚ΜŠg’£","ƒRƒ“ƒsƒ…[ƒ^ƒVƒXƒeƒ€EƒVƒ“ƒ|ƒWƒEƒ€iComSys2016)",,,,,,2016,Nov.
"Ryohei Kobayashi,Tomohiro Misono,Kenji Kise","A High-speed Verilog HDL Simulation Method using a Lightweight Translator","International Symposium on High-Efficient Accelerators ajd Reconfigurable Technologies (Heart 2016)",,,,,"pp. 29-34",2016,July
"–‘‘]–μ ’q—η,‹g£ Œͺ“ρ","PC-FPGA “‡ƒtƒŒ[ƒ€ƒ[ƒN‚Μ”δŠr•]‰Ώ","ξ•ρˆ—Šw‰ο‘ζ‚V‚W‰ρ‘S‘‘ε‰ο",,,,,,2016,Mar.
"μˆδ ”Ž“l,–‘‘]–μ ’q—η,‹g£ Œͺ“ρ","GPGPU-Sim‚Μ•ΐ—ρ‰»","ξ•ρˆ—Šw‰ο‘ζ‚V‚W‰ρ‘S‘‘ε‰ο",,,,,,2016,Mar.
"Yuki Matsuda,Eri Ogawa,Tomohiro Misono,Ryohei Kobayashi,Kenji Kise","Frix: Feasible and Reconfigurable IBM PC Compatible SoC","ξ•ρˆ—Šw‰ο‘ζ‚V‚W‰ρ‘S‘‘ε‰ο",,,,,,2016,Mar.
"Tomohiro Misono,Ryohei Kobayashi,Shimpei Sato,Kenji Kise","Effective Parallel Simulation of ArchHDL under Manycore Environment","International Symposium on Computing and Networking -Across Practical Development and Thieretical Research (CANDAR)",,,,,"pp. 140-146",2015,Dec.
"Eri Ogawa,Yuki Matsuda,Tomohiro Misono,Ryohei Kobayashi,Kenji Kise","Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research","IEEE 9th International Symposium on Embedded Multicore SoCs (MCSoC-15)",,,,,"pp. 65-72",2015,Sept.
"Eri Ogawa,Yuki Matsuda,Tomohiro Misono,Ryohei Kobayashi,Kenji Kise","Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research","IEEE 9th International Symposium on Embedded Multicore SoCs (MCSoC-15)",,,,,"pp. 65-72",2015,Sept.
"Tomohiro Misono,Kenji Kise","System Software Of A Future Computer System With Mesh Interconnect","ξ•ρˆ—Šw‰ο‘ζ‚V‚V‰ρ‘S‘‘ε‰ο",,,,,,2015,Mar.
"Ό“c —T‹M,¬μ ˆ€—,–‘‘]–μ ’q—η,“‘Ž} ’Ό‹P,Žsμ Žόˆκ,‹g£ Œͺ“ρ","MieruSys ƒvƒƒWƒFƒNƒgF•‘”‚ΜFPGA‚π—p‚’‚½ζi“I‚ΘŒvŽZ‹@ƒVƒXƒeƒ€‚ΜŠJ”­","“dŽqξ•ρ’ʐMŠw‰οŒ€‹†•ρRECONF2015",,,,,"pp. 211-216",2015,Jan.