"Stefan Hadjis,Andrew Canis,Ryoya Sobue,Yuko Hara-Azumi,Hiroyuki Tomiyama,Jason Anderson","Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis","Design, Automation & Test in Europe",,,,,,2015,Mar.
"Ittetsu  Taniguchi,Junya Kaida,Takuji Hieda,Yuko Hara-Azumi,Hiroyuki  Tomiyama","Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs",,"IEICE Transactions on Information and Systems",,"vol. E97-D","no. 11","pp. 2827-2834",2014,Nov.
"Yuko Hara-Azumi,Toshihiko Kamata,Ittetsu Taniguchi,Hiroyuki Tomiyama","Yield-Aware Allocation and Binding of Partially-Programmable Functional Units","International Technical Conference on Circuits/Systems, Computers and Communications",,,,,"pp. 729-732",2014,July
"Yuko Hara-Azumi,Toshinobu Matsuba,Hiroyuki Tomiyama,Shinya Honda,Hiroaki Takada","Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 7",,"pp. 37-45",2014,Feb.
"Junya Kaida,Yuko Hara-Azumi,Takuji Hieda,Ittetsu Taniguchi,Hiroyuki Tomiyama,Koji Inoue","Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs",,"IEICE Transactions on Information and Systems",,"vol. E96-D","no. 10","pp. 2268-2271",2013,Oct.
"Yuko Hara-Azumi,Toshinobu Matsuba,Hiroyuki Tomiyama,Shinya Honda,Hiroaki Takada","Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 6",,"pp. 122-126",2013,Aug.
"Ryoya Sobue,Yuko Hara-Azumi,Hiroyuki Tomiyama","Partial Controller Retiming in High-Level Synthesis","Electronic System Level Synthesis Conference",,,,,"pp. 10-15",2013,May
"Yuko Hara-Azumi,Hiroyuki Tomiyama","Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation","International Symposium on Quality Electronic Design",,,,,"pp. 518-523",2013,Mar.
"Yuko Hara,Hiroyuki Tomiyama,Shinya Honda,Hiroaki Takada","Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism",,"IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences",,"vol. E93-A","no. 2","pp. 488-499",2010,Feb.
"Yuko Hara,Hiroyuki Tomiyama,Shinya Honda,Hiroaki Takada","Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis",,"Journal of Information Processing",,"vol. 17",,"pp. 242-254",2009,Oct.
"Seiya Shibata,Shinya Honda,Yuko Hara,Hiroyuki Tomiyama,Hiroaki Takada","Embedded System Covalidation with RTOS Model and FPGA",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 1",,"pp. 126-130",2008,Aug.
"Yuko Hara,Hiroyuki Tomiyama,Shinya Honda,Hiroaki Takada,Katsuya Ishii","Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis",,"IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences",,"vol. E90-A","no. 12","pp. 2853-2862",2007,Dec.
"Yuko Hara,Hiroyuki Tomiyama,Shinya Honda,Hiroaki Takada","Function Call Optimization for Efficient Behavioral Synthesis",,"IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences",,"vol. E90-A","no. 9","pp. 2032-2036",2007,Sept.