"Kota Ando,Jaehoon Yu,Kazutoshi Hirose,Hiroki Nakahara,Kazushi Kawamura,Thiem Van Chu,Masato Motomura","Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner","Hot Chips",,,,,,2021,Aug.
"鈴木 裕太,曽我 尚人,佐藤 真平,中原 啓貴","テーブル参照方式3値ニューラルネットワーク推論プロセッサについて","第33回多値論理とその応用研究会",,,,,,2020,Jan.
"秋元 宏介,佐田 悠生,佐藤 真平,中原 啓貴","ハードウェア実装に適した畳込みニューラルネットワークのフィルタに関する比較",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 373","pp. 61-66",2020,Jan.
"倉持 亮佑,佐田 悠生,下田 将之,佐藤 真平,中原 啓貴","アンサンブル学習を用いたスパースCNNのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 373","pp. 67-72",2020,Jan.
"佐田 悠生,下田 将之,佐藤 真平,中原 啓貴","畳み込みニューラルネットワークを用いた単眼深度推定のFPGA実装について",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 373","pp. 73-78",2020,Jan.
"Ryosuke Kuramochi,Masayuki Shimoda,Youki Sada,Shimpei Sato,Hiroki Nakahara","FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System","The 2019 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2019)",,,,,"pp. 1-5",2019,Dec.
"神宮司明良,佐藤真平,中原啓貴","Wide-SIMDを用いたISAベースのスパースCNNのFPGA実装",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 287","pp. 9-14",2019,Nov.
"Ryosuke Kuramochi,Youki Sada,Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks","IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '19)",,,,,,2019,Oct.
"Naoto Soga,Shimpei Sato,Hiroki Nakahara","Energy-efficient ECG Signals Outlier Detection Hardware using a Sparse Robust Deep Autoencoder","The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2019)",,,,,,2019,Oct.
"鈴木裕太,曽我尚人,佐藤真平,中原啓貴","テーブル参照方式ニューラルネットワーク推論プロセッサにおける2値化と3値化の比較","第42回多値論理フォーラム",,,,"No. 3",,2019,Sept.
"Hiroki Nakahara,Youki Sada,Masayuki Shimoda,Kouki Sayama,Akira Jinguji,Shimpei Sato","FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network",,,,,,,2019,Sept.
"佐山功起,佐藤真平,中原啓貴","深層学習のスパース性を用いた学習高速化手法に関する研究","第42回多値論理フォーラム",,,,"No. 4",,2019,Sept.
"倉持亮佑,下田将之,佐田悠生,佐藤真平,中原啓貴","サーマル画像に対する歩行者検出とそのFPGA実装について",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 208","pp. 31-36",2019,Sept.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 5","pp. 1020-1028",2019,May
"中原啓貴,佐藤真平","電波望遠鏡用デジタル分光器向け畳込みニューラルネットワークを用いた識別機に関して",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 18","pp. 103-108",2019,May
"佐田悠生,下田将之,佐藤真平,中原啓貴","マルチパス構造を持つ意味的領域分割モデルのFPGA実装",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 457","pp. 49-54",2019,May
"Atsuki Munakata,Hiroki Nakahara,Shimpei Sato","Noise Convolutional Neural Networks and FPGA Implementation","The 49th IEEE International Symposium on Multiple-Valued Logic (ISMVL '19)",,,,,,2019,May
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Masayuki Shimoda,Shimpei Sato","GUINNESS: A GUI based Binarized Deep Neural Network Framework for Software Programmers",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 5","pp. 1003-1011",2019,May
"Hiroki Nakahara,Akira Jinguji,Masayuki Shimoda,Shimpei Sato","An FPGA-based Fine Tuning Accelerator for a Sparse CNN","The 27th International Symposium on Field-Programmable Gate Arrays (FPGA '19)",,,,,"pp. 186-186",2019,Feb.
"曽我尚人,佐藤真平,中原啓貴","Sparse Robust Deep Autoencoderによる心電図外れ値検出器のハードウェア向けモデル圧縮について",,"電子情報通信学会技術研究報告",,"vol. 118","no. 457","pp. 127-132",2019,Feb.
"佐田悠生,下田将之,佐藤真平,中原啓貴","Intel社OpenCLを用いた3状態CNNの実装に関して","第32回多値論理とその応用研究会",,,,,,2019,Jan.
"宗形敦樹,佐藤真平,中原啓貴","雑音畳み込みニューラルネットワークとFPGA実装",,"電子情報通信学会技術研究報告",,"vol. 118","no. 432","pp. 19-24",2019,Jan.
"中原啓貴,宗形敦樹,佐藤真平","雑音畳込みニューラルネットワークとその専用回路のFPGA実装に関して","第32回多値論理とその応用研究会",,,,,,2019,Jan.
"曽我尚人,佐藤真平,中原啓貴","Sparse Robust Deep Autoencoderによる心電図外れ値検出器の小型ハードウェアへの実装","第32回多値論理とその応用研究会",,,,,,2019,Jan.
"下田将之,佐藤真平,中原啓貴","ディープニューロ・ファジィによる偽陰性数の削減とその専用回路のFPGA実装の検討","第32回多値論理とその応用研究会",,,,,,2019,Jan.
"神宮司明良,佐藤真平,中原啓貴","Feature-Map Separable Convolutionによる小メモリFPGAでの画像認識の実現",,"電子情報通信学会技術研究報告",,"vol. 118","no. 340","pp. 39-44",2018,Dec.
"Akira Jinguji,Tomoya Fujii,Shimpei Sato,Hiroki Nakahara","An FPGA Realization of OpenPose based on a Sparse Weight Convolutional Neural Network","The 2018 International Conference on Field-Programmable Technology (FPT '18)",,,,,,2018,Dec.
"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector","The 2018 International Conference on Field-Programmable Technology (FPT '18)",,,,,,2018,Dec.
"佐田悠生,下田将之,佐藤真平,中原啓貴","Intel OpenCLを用いた3状態YOLOv2のFPGA実装について",,"電子情報通信学会技術研究報告",,"vol. 118","no. 340","pp. 7-12",2018,Dec.
"曽我尚人,佐藤真平,中原啓貴","Sparse Robust Deep Autoencoderを用いて学習した心電図の外れ値検出器のハードウェア実装について",,"電子情報通信学会技術研究報告",,"vol. 118","no. 340","pp. 45-50",2018,Dec.
"宗形敦樹,佐藤真平,中原啓貴","摂動を考慮した畳み込みニューラルネットワークについて","第41回 多値論理フォーラム",,,,,,2018,Sept.
"曽我尚人,佐藤真平,中原啓貴","Robust Deep Autoencoderを用いた心電図の外れ値検出","第41回 多値論理フォーラム",,,,,,2018,Sept.
"中原啓貴,下田将之,佐藤真平","重み3状態ディープニューラルネットワークを用いた一般物体アルゴリズムYOLOv2のFPGA実装法について","第41回 多値論理フォーラム",,,,,,2018,Sept.
"Haoxuan Cheng,Shimpei Sato,Hiroki Nakahara","A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS)",,"電子情報通信学会技術研究報告",,"vol. 118","no. 215","pp. 19-22",2018,Sept.
"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2)","The 28th International Conference on Field-programmable Logic and Applications (FPL 2018)",,,,,,2018,Aug.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Demonstration of Object Detection for an event-driven camera","The 28th International Conference on Field-programmable Logic and Applications (FPL 2018)",,,,,,2018,Aug.
"下田将之,佐藤真平,中原啓貴","ディープニューロ・ファジィによる偽陰性数の削減とそのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 165","pp. 211-216",2018,July
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Power Efficient Object Detector with an Event-Driven Camera on an FPGA","The 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2018)",,,,,,2018,June
"Haoxuan Cheng,Shimpei Sato,Hiroki Nakahara","A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System","The 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2018)",,,,,,2018,June
"下田将之,佐藤真平,中原啓貴","イベント駆動カメラを用いた物体検出システムのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 63","pp. 81-86",2018,May
"中原啓貴,下田将之,佐藤真平","3状態CNNを用いたYOLOv2のFPGA実現に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 63","pp. 87-92",2018,May
"Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara","A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor","The 48th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2018)",,,,,"pp. 174-179",2018,May
"Kota Ando,Kodai Ueyoshi,Kentaro Orimo,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Shinya Takamaeda-Yamazaki,Masayuki Ikebe,Tetsuya Asai,Tadahiro Kuroda,Masato Motomura","BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W",,"IEEE Journal of Solid-State Circuits",,"Vol. 53","No. 4","pp. 983-994",2018,Apr.
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara","A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolutional Neural Network on an FPGA","The 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018)",,,,,,2018,Mar.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Shimpei Sato","A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA","The 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018)",,,,,,2018,Feb.
"Akira Jinguji,Shimpei Sato,Hiroki Nakahara","An FPGA Realization of a Random Forest with k-means Clustering using a High-level Synthesis Design",,"IEICE Transactions on Information and Systems",,"Vol. E101-D","No. 2","pp. 354-362",2018,Feb.
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara","A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA",,"IEICE Transactions on Information and Systems",,"Vol. E101-D","No. 2","pp. 376-386",2018,Feb.
"下田将之,佐藤真平,中原啓貴","ディープニューロファジィの性能評価に関して","第31回多値論理とその応用研究会",,,,,,2018,Jan.
"米川晴義,佐藤真平,中原啓貴","重み3値入出力2値ディープニューラルネットワークの学習と組込みプロセッサ実現について","第31回多値論理とその応用研究会",,,,,,2018,Jan.
"藤井智也,佐藤真平,中原啓貴","FPGA向けの2値化畳み込みニューラルネットワークのニューロン刈りアルゴリズムについて","第31回多値論理とその応用研究会",,,,,,2018,Jan.
"下田将之,佐藤真平,中原啓貴","全2値化畳み込みニューラルネットワークとそのFPGA実装について ? FPT2017デザインコンテスト参加報告 ?",,"電子情報通信学会技術研究報告",,"vol. 117","no. 379","pp. 7-11",2018,Jan.
"宇山拓夢,藤井智也,米川晴義,佐藤真平,中原啓貴","Intel OpenCLを用いたディープニューラルネットワークのFPGA実現に関して",,"電子情報通信学会技術研究報告",,"vol. 117","no. 379","pp. 13-18",2018,Jan.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","All Binarized Convolutional Neural Network and Its implementation on an FPGA","The International Conference on Field-Programmable Technology (FPT 2017)",,,,,"pp. 291-294",2017,Dec.
"Hiroki Nakahara,Haruyoshi Yonekawa,Shimpei Sato","An Object Detector based on Multiscale Sliding Window Search using a Fully Pipelined Binarized CNN on an FPGA","The International Conference on Field-Programmable Technology (FPT 2017)",,,,,"pp. 168-175",2017,Dec.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Masayuki Shimoda,Shimpei Sato","GUINNESS: A GUI based neural network synthesizer for an FPGA","The 27th International Conference on Field-programmable Logic and Applications (FPL 2017)",,,,,,2017,Sept.
"Hiroki Nakahara,Tomoya Fujii,Shimpei Sato","A Fully Connected Layer Elimination for a Binarized Convolutional Neural Network on an FPGA","The 27th International Conference on Field-programmable Logic and Applications (FPL 2017)",,,,,"pp. 1-4",2017,Sept.
"Kota Ando,Kodai Ueyoshi,Kazutoshi Hirose,Kentaro Orimo,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Masayuki Ikebe,Shinya Takamaeda-Yamazaki,Tetsuya Asai,Tadahiro Kuroda,Masato Motomura","In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks","The 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017)",,,,,"pp. 116-119",2017,Aug.
"Kota Ando,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Masato Motomura","BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS","2017 Symposia on VLSI Technology and Circuits",,,,,,2017,June
"Hiroki Nakahara,Akira Jinguji,Shimpei Sato,Tsutomu Sasao","A Random Forest using a Multi-valued Decision Diagram on an FPGA","The 47th IEEE International Symposium on Multiple-valued Logic (ISMVL 2017)",,,,,,2017,May
"Haruyoshi Yonekawa,Hiroki Nakahara","An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA","24th Reconfigurable Architectures Workshop (RAW 2017)",,,,,,2017,May
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara,Masato Motomura","An FPGA Realization of a Deep Convolutional Neural Network using a Threshold Neuron Pruning","International Symposium on Applied Reconfigurable Computing (ARC2017)",,,,,,2017,Apr.
"中原 啓貴,井上 一成,中田 秀基","ネットワーク検索エンジン及びディープニューラルネットワークの高速化",,"電子情報通信学会学会誌 FPGAを用いた計算処理の高速化技術小特集",,"Vol. 100","No. 2","pp. 87-91",2017,Feb.
"Hiroki Nakahara,Haruyoshi Yonekawa,Hisashi Iwamoto,Masato Motomura","A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA","International Symposium on Field-Programmable Gate Array (FPGA2017)",,,,,,2017,Feb.
"米川 晴義,中原 啓貴,本村 真人","ディープニューラルネットワークの2値化と3値化の比較","多値論理研究会",,,,,,2017,Jan.
"米川晴義,中原啓貴,本村真人","電力性能効率に優れた二値化ディープニューラルネットワークのFPGA実装","電子情報通信学会リコンフィギャラブルシステム研究会",,,,,,2017,Jan.
"藤井智也,佐藤真平,中原啓貴,本村真人","畳込みニューラルネットワークのニューロン刈りによるメモリ量削減とFPGA実現について","電子情報通信学会リコンフィギャラブルシステム研究会",,,,,,2017,Jan.
"神宮司明良,佐藤真平,中原啓貴","特徴空間の分割にk平均法を導入したランダムフォレストのFPGA実装","第30回多値論理とその応用研究会",,,,,,2017,Jan.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tsutomu Sasao,Hisashi Iwamoto,Masato Motomura","A Memory-Based Realization of a Binarized Deep Convolutional Neural Network","The International Conference on Field-Programmable Technology (FPT 2016),",,,,,,2016,Dec.
"Hiroki Nakahara,Tsutomu Sasao,Hiroyuki Nakanishi,Kazumasa Iwai","An FFT circuit based on Nested RNS using Constant Division Algorithm",,"ACM SIGARCH Computer Architecture News",,"Vol. 44","No. 4","pp. 44-49",2016,Dec.
"Hiroki Nakahara,Akira Jinguji,Tomoya Fujii,Shimpei Sato","An Acceleration of a Random Forest Classification using Altera SDK for OpenCL","The International Conference on Field-Programmable Technology (FPT 2016)",,,,,,2016,Dec.
"Takahisa Kurose,Hiroki Nakahara,Shimpei Sato,Tetsuya Morimoto","A Low-Power Intelligent Camera using an FPGA toward Internet of Things Agriculture","The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016),",,,,,,2016,Oct.
"中原啓貴,神宮司明良,佐藤真平,笹尾勤,丸山直也","多値決定グラフを用いたランダムフォレストに関して","第39回 多値論理フォーラム",,,,,,2016,Sept.
"Hiroki Nakahara,Tsutomu Sasao,Hiroyuki Nakanishi,Kazumasa Iwai","An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope","The 46th IEEE International Symposium on Multiple-valued Logic (ISMVL 2016)",,,,,,2016,May
"Hiroki Nakahara,Tsutomu Sasao,Munehiro Matsuura,Hisashi Iwamoto","LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification",,"IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)",,"Vol. 6","No. 1","pp. 73-86",2016,Mar.
"Hiroki Nakahara,Tsutomu Sasao,Munehiro Matsuura,Hisashi Iwamoto","An Update Method for a Low Power CAM Emulator using an LUT Cascade Based on an EVMDD (k)",,"Journal of Multiple-Valued Logic and Soft Computing",,"Vol. 26","No. 1-2","pp. 109-123",2016,Feb.