"Žü“¡ —I‰î,Shuichiro Yamamoto,‰î�ì —T�Í,Wen ZhenChao,’†�ª —¹�¹,ŽO’J �½Ži,“c’† ‰ë–¾,’––“ �_ˆê˜Y,�›Œ´ ‘�","ƒiƒmCMOSƒfƒoƒCƒX‚ð—p‚¢‚½‹[Ž—ƒXƒsƒ“MOSFET‚Ì�ÝŒv‚Æ�«”\ (ƒVƒŠƒRƒ“�Þ—¿�EƒfƒoƒCƒX�EIEDM“Á�W(�æ’[CMOSƒfƒoƒCƒX�Eƒvƒ�ƒZƒX‹Z�p))",,"“dŽq�î•ñ’Ê�MŠw‰ï‹Z�pŒ¤‹†•ñ�� : �MŠw‹Z•ñ","ˆê”ÊŽÐ’c–@�l“dŽq�î•ñ’Ê�MŠw‰ï","Vol. 112","No. 421","pp. 43-46",2013,Jan.
"Shuichiro Yamamoto,Shuto, Y.,Sugahara, S.","Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic",,"EPJ Applied Physics",,"Vol. 63","No. 1",,2013,
"Nakane, R.,Shuto, Y.,Sukegawa, H.,Wen, Z.C.,Shuichiro Yamamoto,Mitani, S.,Tanaka, M.,Inomata, K.,Sugahara, S.","Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service",,"European Solid-State Device Research Conference",,,,"pp. 272-275",2013,
"Shuto, Y.,Shuichiro Yamamoto,Sugahara, S.","FinFET-based pseudo-spin-transistor: Design and performance",,"2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013",,,,,2013,