"Y. Takamura,Y. Shuto,S. Yamamoto,H. Funakubo,M. Kurosawa,S. Nakagawa,S. Sugahara","Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM",,"Solid-State Electron.",,"vol. 128","no. Supplement C","pp. 194-199",2016,Oct.
"Y. Shuto,S. Yamamoto,S. Sugahara","Energy Performance of Nonvolatile Power-Gating SRAM Using SOTB Technology","46th European Solid-State Device Conference",,,,,,2016,Sept.
"Y. Shuto,S. Yamamoto,S. Sugahara","Design and Implementation of Nonvolatile Power-Gating SRAM Using SOTB Technology","International Symposium on Low Power Electronics and Design, San Francisco",,,,,,2016,Aug.
"Y. Shuto,S. Yamamoto,S. Sugahara","Nonvolatile Power-gating Architecture for SRAM using SOTB Technology","016 IEEE Silicon Nanoelectronics Workshop (SNW 2016)",,,,,,2016,June
"Y. Shuto,S. Yamamoto,S. Sugahara","New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM","29th IEEE International Conference on Microelectronic Test Structures (ICMTS)",,,"  8-1",,,2016,Mar.
"Y. Takamura,Y. Shuto,S. Yamamoto,H. Funakubo,M.K. Kurosawa,S. Nakagawa,S. Sugahara","Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAMs","2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)",,,,"pp. 72-75",2016,Jan.
"Sugahara, S.,Shuto, Y.,Shuichiro Yamamoto","Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems",,"Nanomagnetic Devices and Phenomena for Energy-Efficient Computing",,,,"pp. 65-90",2016,