"W. Zhang,S. Netsu,T.Kanazawa,T. Amemiya,Y. Miyamoto","p-MoS2/HfS2 van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO2 Dielectric","2018 International Conference on Solid State Devices and Materials (SSDM 2018)",,,,,"  M-7-03",2018,Sept.
"Shinjiro Iwata,Kazumi Ohashi,Netsu Seikou,Koichi Fukuda,YASUYUKI MIYAMOTO","GaAsSb/InGaAsヘテロ接合を用いたダブルゲートトンネルFETにおける界面準位の導入による性能の劣化","第76回応用物理学会秋季学術講演会",,,,,"  16a-1C-6",2018,Sept.
"Wenlun Zhang,Netsu Seikou,Toru Kanazawa,Tomohiro Amemiya,YASUYUKI MIYAMOTO","埋め込みNiバックゲートを用いたp-MoS2/HfS2トンネルFET","第79回応用物理学会秋季学術講演会",,,,,"  19a-212B-5",2018,Sept.
"Seiko Netsu,Toru Kanazawa,Teerayut Uwanno,Tomohiro Amemiya,Kosuke Nagashio,Yasuyuki Miyamoto","Type-II HfS2/MoS2 Heterojunction Transistors",,"IEICE Transactions on Electronics",,"Vol. E101-C","No. 5","pp. 338-342",2018,May
"S. Netsu,M. Hellenbrand,C. B. Zota,Y. Miyamoto,E. Lind","A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs",,"IEEE Journal of the Electron Devices Society",,"Vol. 6","  issue. 1","pp. 408-412 (2018).",2018,Feb.