"Hiroki Nakahara,Haruyoshi Yonekawa,Shimpei Sato","An Object Detector based on Multiscale Sliding Window Search using a Fully Pipelined Binarized CNN on an FPGA","The International Conference on Field-Programmable Technology (FPT 2017)",,,,,"pp. 168-175",2017,Dec.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","All Binarized Convolutional Neural Network and Its implementation on an FPGA","The International Conference on Field-Programmable Technology (FPT 2017)",,,,,"pp. 291-294",2017,Dec.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Masayuki Shimoda,Shimpei Sato","GUINNESS: A GUI based neural network synthesizer for an FPGA","The 27th International Conference on Field-programmable Logic and Applications (FPL 2017)",,,,,,2017,Sept.
"Hiroki Nakahara,Tomoya Fujii,Shimpei Sato","A Fully Connected Layer Elimination for a Binarized Convolutional Neural Network on an FPGA","The 27th International Conference on Field-programmable Logic and Applications (FPL 2017)",,,,,"pp. 1-4",2017,Sept.
"Kota Ando,Kodai Ueyoshi,Kazutoshi Hirose,Kentaro Orimo,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Masayuki Ikebe,Shinya Takamaeda-Yamazaki,Tetsuya Asai,Tadahiro Kuroda,Masato Motomura","In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks","The 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017)",,,,,"pp. 116-119",2017,Aug.
"Kota Ando,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Masato Motomura","BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS","2017 Symposia on VLSI Technology and Circuits",,,,,,2017,June
"Haruyoshi Yonekawa,Hiroki Nakahara","An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA","24th Reconfigurable Architectures Workshop (RAW 2017)",,,,,,2017,May
"Hiroki Nakahara,Akira Jinguji,Shimpei Sato,Tsutomu Sasao","A Random Forest using a Multi-valued Decision Diagram on an FPGA","The 47th IEEE International Symposium on Multiple-valued Logic (ISMVL 2017)",,,,,,2017,May
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara,Masato Motomura","An FPGA Realization of a Deep Convolutional Neural Network using a Threshold Neuron Pruning","International Symposium on Applied Reconfigurable Computing (ARC2017)",,,,,,2017,Apr.
"Hiroki Nakahara,井上 一成,中田 秀基","ネットワーク検索エンジン及びディープニューラルネットワークの高速化",,"電子情報通信学会学会誌 FPGAを用いた計算処理の高速化技術小特集",,"Vol. 100","No. 2","pp. 87-91",2017,Feb.
"Hiroki Nakahara,Haruyoshi Yonekawa,Hisashi Iwamoto,Masato Motomura","A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA","International Symposium on Field-Programmable Gate Array (FPGA2017)",,,,,,2017,Feb.
"Haruyoshi Yonekawa,Hiroki Nakahara,本村真人","電力性能効率に優れた二値化ディープニューラルネットワークのFPGA実装","電子情報通信学会リコンフィギャラブルシステム研究会",,,,,,2017,Jan.
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara,本村真人","畳込みニューラルネットワークのニューロン刈りによるメモリ量削減とFPGA実現について","電子情報通信学会リコンフィギャラブルシステム研究会",,,,,,2017,Jan.
"Haruyoshi Yonekawa,Hiroki Nakahara,本村 真人","ディープニューラルネットワークの2値化と3値化の比較","多値論理研究会",,,,,,2017,Jan.
"Akira Jinguji,Shimpei Sato,Hiroki Nakahara","特徴空間の分割にk平均法を導入したランダムフォレストのFPGA実装","第30回多値論理とその応用研究会",,,,,,2017,Jan.