"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector","The 2018 International Conference on Field-Programmable Technology (FPT '18)",,,,,,2018,Dec.
"Youki Sada,Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Intel OpenCLを用いた3状態YOLOv2のFPGA実装について",,"電子情報通信学会技術研究報告",,"vol. 118","no. 340","pp. 7-12",2018,Dec.
"Akira Jinguji,Shimpei Sato,Hiroki Nakahara","Feature-Map Separable Convolutionによる小メモリFPGAでの画像認識の実現",,"電子情報通信学会技術研究報告",,"vol. 118","no. 340","pp. 39-44",2018,Dec.
"Naoto Soga,Shimpei Sato,Hiroki Nakahara","Sparse Robust Deep Autoencoderを用いて学習した心電図の外れ値検出器のハードウェア実装について",,"電子情報通信学会技術研究報告",,"vol. 118","no. 340","pp. 45-50",2018,Dec.
"Akira Jinguji,Tomoya Fujii,Shimpei Sato,Hiroki Nakahara","An FPGA Realization of OpenPose based on a Sparse Weight Convolutional Neural Network","The 2018 International Conference on Field-Programmable Technology (FPT '18)",,,,,,2018,Dec.
"Naoto Soga,Shimpei Sato,Hiroki Nakahara","Robust Deep Autoencoderを用いた心電図の外れ値検出","第41回 多値論理フォーラム",,,,,,2018,Sept.
"Haoxuan Cheng,Shimpei Sato,Hiroki Nakahara","A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS)",,"電子情報通信学会技術研究報告",,"vol. 118","no. 215","pp. 19-22",2018,Sept.
"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","重み3状態ディープニューラルネットワークを用いた一般物体アルゴリズムYOLOv2のFPGA実装法について","第41回 多値論理フォーラム",,,,,,2018,Sept.
"Atsuki Munakata,Shimpei Sato,Hiroki Nakahara","摂動を考慮した畳み込みニューラルネットワークについて","第41回 多値論理フォーラム",,,,,,2018,Sept.
"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2)","The 28th International Conference on Field-programmable Logic and Applications (FPL 2018)",,,,,,2018,Aug.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Demonstration of Object Detection for an event-driven camera","The 28th International Conference on Field-programmable Logic and Applications (FPL 2018)",,,,,,2018,Aug.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","ディープニューロ・ファジィによる偽陰性数の削減とそのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 165","pp. 211-216",2018,July
"Haoxuan Cheng,Shimpei Sato,Hiroki Nakahara","A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System","The 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2018)",,,,,,2018,June
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","Power Efficient Object Detector with an Event-Driven Camera on an FPGA","The 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2018)",,,,,,2018,June
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","イベント駆動カメラを用いた物体検出システムのFPGA実装に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 63","pp. 81-86",2018,May
"Hiroki Nakahara,Masayuki Shimoda,Shimpei Sato","3状態CNNを用いたYOLOv2のFPGA実現に関して",,"電子情報通信学会技術研究報告",,"vol. 118","no. 63","pp. 87-92",2018,May
"Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara","A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor","The 48th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2018)",,,,,"pp. 174-179",2018,May
"Kota Ando,Kodai Ueyoshi,Kentaro Orimo,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara,Shinya Takamaeda-Yamazaki,Masayuki Ikebe,Tetsuya Asai,Tadahiro Kuroda,Masato Motomura","BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W",,"IEEE Journal of Solid-State Circuits",,"Vol. 53","No. 4","pp. 983-994",2018,Apr.
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara","A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolutional Neural Network on an FPGA","The 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018)",,,,,,2018,Mar.
"Akira Jinguji,Shimpei Sato,Hiroki Nakahara","An FPGA Realization of a Random Forest with k-means Clustering using a High-level Synthesis Design",,"IEICE Transactions on Information and Systems",,"Vol. E101-D","No. 2","pp. 354-362",2018,Feb.
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara","A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA",,"IEICE Transactions on Information and Systems",,"Vol. E101-D","No. 2","pp. 376-386",2018,Feb.
"Hiroki Nakahara,Haruyoshi Yonekawa,Tomoya Fujii,Shimpei Sato","A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA","The 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018)",,,,,,2018,Feb.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","全2値化畳み込みニューラルネットワークとそのFPGA実装について ? FPT2017デザインコンテスト参加報告 ?",,"電子情報通信学会技術研究報告",,"vol. 117","no. 379","pp. 7-11",2018,Jan.
"Takumu Uyama,Tomoya Fujii,Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara","Intel OpenCLを用いたディープニューラルネットワークのFPGA実現に関して",,"電子情報通信学会技術研究報告",,"vol. 117","no. 379","pp. 13-18",2018,Jan.
"Haruyoshi Yonekawa,Shimpei Sato,Hiroki Nakahara","重み3値入出力2値ディープニューラルネットワークの学習と組込みプロセッサ実現について","第31回多値論理とその応用研究会",,,,,,2018,Jan.
"Tomoya Fujii,Shimpei Sato,Hiroki Nakahara","FPGA向けの2値化畳み込みニューラルネットワークのニューロン刈りアルゴリズムについて","第31回多値論理とその応用研究会",,,,,,2018,Jan.
"Masayuki Shimoda,Shimpei Sato,Hiroki Nakahara","ディープニューロファジィの性能評価に関して","第31回多値論理とその応用研究会",,,,,,2018,Jan.