"Eiji YOSHIYA,Tomoya NAKANISHI,Tsuyoshi ISSHIKI","Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E105.A","No. 7","  1061-1069",2022,July
"Eiji Yoshiya,Tomoya Nakanishi,Tsuyoshi Isshiki","RTL Design Framework for Embedded Processor by using C++ Description","Design, Automation and Test in Europe Conference (DATE)",,,,,,2021,Feb.