"Satoru Jimbo,Daiki Okonogi,Kota Ando,Thiem Van Chu,Jaehoon Yu,Masato Motomura,Kazushi Kawamura","A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers",,"IEICE Transactions on Information and Systems",,"Vol. E105-D","No. 12",,2022,Dec.
"Yasuyuki Okoshi,Angel Lopez Garcia-Arias,Kazutoshi Hirose,Kota Ando,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","Multicoated Supermasks Enhance Hidden Networks","International Conference on Machine Learning",,,,,,2022,July
"Kazutoshi Hirose,Jaehoon Yu,Kota Ando,Yasuyuki Okoshi,Angel Lopez Garcia-Arias,Junnosuke Suzuki,Thiem Van Chu,Kazushi Kawamura,Masato Motomura","Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet",,"International Solid-State Circuits Conference",,,,,2022,Feb.
"Thiem Van Chu,Ryuichi Kitajima,Kazushi Kawamura,Jaehoon Yu,Masato Motomura","A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning","International Conference on Field-Programmable Technology",,,,,,2021,Dec.
"Angel Lopez Garcia-Arias,Masanori Hashimoto,Masato Motomura,Jaehoon Yu","Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks","The British Machine Vision Conference",,,,,,2021,Nov.
"Kota Ando,Jaehoon Yu,Kazutoshi Hirose,Hiroki Nakahara,Kazushi Kawamura,Thiem Van Chu,Masato Motomura","Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner","Hot Chips",,,,,,2021,Aug.
"Junnosuke Suzuki,Tomohiro Kaneko,Kota Ando,Kazutoshi Hirose,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation",,"International Journal of Networking and Computing",,,,,2021,July
"Shungo Kumazawa,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training",,"International Journal of Networking and Computing",,,,,2021,July
"Kazutoshi Hirose,Shinya Takamaeda-Yamazaki,Jaehoon Yu,Masato Motomura","Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture",,"IEEE Access",,"Vol. 9",,"pp. 6179-6187",2021,Jan.
"Junnosuke Suzuki,Kota Ando,Kazutoshi Hirose,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation","International Symposium on Computing and Networking (CANDAR)",,,,,,2020,Nov.
"Shungo Kumazawa,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training","International Symposium on Computing and Networking (CANDAR)",,,,,,2020,Nov.
"本村 真人,高前田信也,植吉 晃大,安藤 洸太,廣? 一俊","深層ニューラルネットワーク向けプロセッサ技術の実例と展望",,"電子情報通信学会和文論文誌C",,"Vol. J103-C","No. 05",,2020,May
"Taiga Ikeda,Kento Sakurada,Atsuyoshi Nakamura,Masato Motomura,Shinya Takamaeda-Yamazaki","Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs","16th International Symposium on Applied Reconfigurable Computing (ARC 2020)",,,,,,2020,Apr.
"Yafei Ou,Prasoon Ambalathankandy,Masayuki Ikebe,Shinya Takamaeda,Masato Motomura,Tetsuya Asai","Real-time Tone Mapping: A State of the Art Report",,"IEEE TCSVT",,,,,2020,Mar.
"本村 真人","「Q&Aで分かるAIチップ」",,"週刊エコノミスト 2020年2月4日号",,,,,2020,Feb.
"Yamamoto K.,Ando K.,Metrig N.,Takemoto T.,Teramoto H.,Sakai A.,Takamaeda-Yamazaki S.,Motomura M.","STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions","2020 IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2020,Feb.
"平山 侑樹,浅井 哲也,本村 真人,高前田 伸也","決定論的変分推論に基づくベイジアンCNNの検討","人工知能学会 第111回人工知能基本問題研究会(SIG-FPAI)",,,,,,2020,Jan.
"Prasoon Ambalathankandy,Yafei Ou,Jyotsna Kochiyil,Shinya Takamaeda-Yamazaki,Masato Motomura,Tetsuya Asai,Masayuki Ikebe","Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band","2019 International Conference on Digital Image Computing: Techniques and Applications",,,,,,2019,Dec.
"本村 真人","AIエッジコンピューティングへの希望と展望",,"OKIテクニカルレビュー、「AIエッジコンピューティングが拓く高度IoT社会」特集",,,,,2019,Dec.
"Kodai Ueyoshi,Ryota Uematsu,Takumi Kudo,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Kota Ando,Kodai Ueyoshi,Yuka Oba,Kazutoshi Hirose,Ryota Uematsu,Takumi Kudo,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Masato Motomura","Dither NN: hardware/algorithm co-design for accurate quantized neural networks",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 12",,2019,Dec.
"Kasho Yamamoto,Masayuki Ikebe,Tetsuya Asai,Masato Motomura,Shinya Takamaeda-Yamazaki","FPGA-based annealing processor with time-division multiplexing",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 12",,2019,Dec.
"Masato Motomura","AI Computing: The Promised Land for Computer Architecture Innovation","Future Chips Forum 2019",,,,,,2019,Dec.
"Yuki Hirayama,Tetsuya Asai,Masato Motomura,Shinya Takamaeda-Yamazaki","A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators","The 7th International Symposium on Computing and Networking (CANDAR 2019)",,,,,,2019,Nov.
"Masato Motomura","AI Computing: What it is about & How hardware can help it out","Asian Solid-State Circuit Conference (A-SSCC)",,,,,,2019,Oct.
"Tatsuya Kaneko,Kentaro Orimo,Itaru Hida,Shinya Takamaeda-Yamazaki,Masayuki Ikebe,Masato Motomura,Tetsuya Asai","A Study on a Low Power Optimization Algorithm for an Edge-AI Device",,"IEICE Transactions on Nonlinear Theory and Its Applications,",,"Vol. 10","No. 4",,2019,Oct.
"本村 真人","AIチップ: 世界の研究動向と東工大の研究戦略","科学技術創成研究院公開",,,,,,2019,Oct.
"本村 真人","AI関連半導体技術の動向","HAB研セミナー",,,,,,2019,Aug.
"平山 侑樹,廣瀬 一俊,安藤 洸太,植吉 晃大,浅井 哲也,本村 真人,高前田 伸也","ベイジアンNNのHW実装に向けたサンプリング手法の検討","電子情報通信学会研究会報告CPSY2019-35",,,,,,2019,July
"Prasoon Ambalathankandy,Masayuki Ikebe,Takashi Yoshida,Takeshi Shimada,Shinya Takamaeda-Yamazaki,Masato Motomura","An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA",,"IEEE Transactions on Circuits and Systems for Video Technology",,"Vol. 29",,,2019,July
"Yuka Oba,Kota Ando,Tetsuya Asai,Masato Motomura,Shinya Takamaeda-Yamazaki","DeltaNet: Differential Binary Neural Networ","IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2019)",,,,,,2019,July
"本村 真人","AIチップの世界動向と日本がとるべき戦略","EPFCシンポジウム",,,,,,2019,July
"大羽 由華,村上 大輔,中江 達哉,安藤 洸太,浅井 哲也,本村 真人,高前田 伸也","二値化ニューラルネットワークのハードウェア指向精度向上手法の検討","電子情報通信学会研究会報告CPSY2019-8",,,,,,2019,June
"廣瀬 一俊,浅井 哲也,本村 真人,高前田 伸也","エッジ環境におけるニューラルネットワーク学習軽量化手法の検討","電子情報通信学会研究会報告CPSY2019-7",,,,,,2019,June
"池田 泰我,植吉 晃大,安藤 洸太,廣瀬 一俊,浅井 哲也,本村 真人,高前田 伸也","効率的なDNN計算のための無効ニューロン予測手法の評価","情報処理学会システム・アーキテクチャ研究会",,,,,,2019,June
"7.	安藤 洸太,植吉 晃大,大羽 由華,工藤 巧,池辺 将之,浅井 哲也,高前田 伸也,安藤 洸太,植吉 晃大,大羽 由華,廣瀬 一俊,工藤 巧,池辺 将之,浅井 哲也,高前田 伸也,本村 真人","Dither NN: 画像処理から着想を得た組込み向け量子化ニューラルネットワークの精度向上手法","電子情報通信学会研究会報告RECONF2019-14",,,,,,2019,May
"金子 竜也,高前田 伸也,本村 真人,浅井 哲也","オンライン学習を行う階層型ニューラルネットワークハードウェアの低電力化に向けた三値バックプロパゲーション法の提案","LSIとシステムのワークショップ2019",,,,,,2019,May
"植吉 晃大,池田 泰我,安藤 洸太,廣瀬 一俊,浅井 哲也,高前田 伸也,本村 真人","無効ニューロン予測によるDNN計算効率化手法","電子情報通信学会研究会報告RECONF2019-18",,,,,,2019,May
"本村 真人","コンピューティングアーキテクチャ",,"JST CRDS 研究開発の俯瞰報告書 2019年版",,,,,2019,Mar.
"Masato Motomura","AI Computing: The Promised Land for Hardware?","Multimedia Workshop 2019",,,,,,2019,Mar.
"Masato Motomura","Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures","Riken International Workshop on Neuromorphic Computing (R-WoNC’19)",,,,,,2019,Mar.
"Minamikawa K.,Takamaeda-Yamazaki S.,Ikebe M.,Motomura M.,Asai T.","FPGA-based FORCE learning accelerator towards real-time online reservoir computing","2019 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing",,,,,,2019,Mar.
"Suzuki S.,Rim S.,Takamaeda-Yamazaki S.,Ikebe M.,Motomura M.,Asai T.","Experimental demonstration of physical reservoir computing with nonlinear electronic devices","2019 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing",,,,,,2019,Mar.
"Kaneko T.,Ikebe M.,Takamaeda-Yamazaki S.,Motomura M.,Asai T.","Hardware-oriented algorithm and architecture for generative adversarial networks","2019 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing",,,,,,2019,Mar.
"Kaneko T.,Ikebe M.,Takamaeda-Yamazaki S.,Motomura M.,Asai T.","Ternarized backpropagation: a hardware-oriented optimization algorithm for edge-oriented AI devices","The 7th RIEC International Symposium on Brain Functions and Brain Computer",,,,,,2019,Feb.
"Rim S.,Suzuki S.,Takamaeda-Yamazaki S.,Ikebe M.,Motomura M.,Asai T.","Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits","The 7th Japan-Korea Joint Workshop on Complex Communication Sciences",,,,,,2019,Jan.
"本村 真人","深層学習プロセッサの展望",,"映像メディア学会誌「データ科学を支えるアクセラレーション技術」特集",,,,,2019,Jan.
"本村 真人","AIハードウェアの必要性と期待 ? 世界的大競争の中で ?","AIチップ設計拠点設立記念シンポジウム",,,,,,2019,Jan.
"Ueyoshi K.,Ando K.,Hirose K,Takamaeda-Yamazaki S.,Hamada M.,Kurorda T.,Motomura M.","QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3D SRAM Using Inductive Coupling Technology in 40-nm CMOS",,"IEEE Journal of Solid-State Circuits",,"Vol. 54","No. 1",,2019,Jan.
"高前田 伸也,植松 瞭太,藤澤 慎也,藤崎 修一,本村 真人","ディープニューラルネットワーク向け拡張可能な高位合成コンパイラの開発 月","電子情報通信学会リコンフィギャラブルシステム研究会",,,,,,2019,Jan.