"Satoru Jimbo,Daiki Okonogi,Kota Ando,Thiem Van Chu,Jaehoon Yu,Masato Motomura,Kazushi Kawamura","A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers",,"IEICE Transactions on Information and Systems",,"Vol. E105-D","No. 12",,2022,Dec.
"Yasuyuki Okoshi,Angel Lopez Garcia-Arias,Kazutoshi Hirose,Kota Ando,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","Multicoated Supermasks Enhance Hidden Networks","International Conference on Machine Learning",,,,,,2022,July
"Kazutoshi Hirose,Jaehoon Yu,Kota Ando,Yasuyuki Okoshi,Angel Lopez Garcia-Arias,Junnosuke Suzuki,Thiem Van Chu,Kazushi Kawamura,Masato Motomura","Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet",,"International Solid-State Circuits Conference",,,,,2022,Feb.
"Kota Ando,Jaehoon Yu,Kazutoshi Hirose,Hiroki Nakahara,Kazushi Kawamura,Thiem Van Chu,Masato Motomura","Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner","Hot Chips",,,,,,2021,Aug.
"Junnosuke Suzuki,Tomohiro Kaneko,Kota Ando,Kazutoshi Hirose,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation",,"International Journal of Networking and Computing",,,,,2021,July
"Kota Ando","A Study of Highly Compact and Efficient Neural Network Accelerators through Architecture/Algorithm Co-Exploration",,,,,,,2021,Mar.
"Kota Ando","A Study of Highly Compact and Efficient Neural Network Accelerators through Architecture/Algorithm Co-Exploration",,,,,,,2021,Mar.
"Kota Ando","A Study of Highly Compact and Efficient Neural Network Accelerators through Architecture/Algorithm Co-Exploration",,,,,,,2021,Mar.
"Junnosuke Suzuki,Kota Ando,Kazutoshi Hirose,Kazushi Kawamura,Thiem Van Chu,Masato Motomura,Jaehoon Yu","ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation","International Symposium on Computing and Networking (CANDAR)",,,,,,2020,Nov.
"本村 真人,高前田信也,植吉 晃大,安藤 洸太,廣? 一俊","深層ニューラルネットワーク向けプロセッサ技術の実例と展望",,"電子情報通信学会和文論文誌C",,"Vol. J103-C","No. 05",,2020,May
"Yamamoto K.,Ando K.,Metrig N.,Takemoto T.,Teramoto H.,Sakai A.,Takamaeda-Yamazaki S.,Motomura M.","STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions","2020 IEEE International Solid-State Circuits Conference (ISSCC)",,,,,,2020,Feb.
"Kodai Ueyoshi,Ryota Uematsu,Takumi Kudo,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Kota Ando,Kodai Ueyoshi,Yuka Oba,Kazutoshi Hirose,Ryota Uematsu,Takumi Kudo,Masayuki Ikebe,Tetsuya Asai,Shinya Takamaeda-Yamazaki,Masato Motomura","Dither NN: hardware/algorithm co-design for accurate quantized neural networks",,"IEICE Transactions on Information and Systems",,"Vol. E102-D","No. 12",,2019,Dec.
"平山 侑樹,廣瀬 一俊,安藤 洸太,植吉 晃大,浅井 哲也,本村 真人,高前田 伸也","ベイジアンNNのHW実装に向けたサンプリング手法の検討","電子情報通信学会研究会報告CPSY2019-35",,,,,,2019,July
"Yuka Oba,Kota Ando,Tetsuya Asai,Masato Motomura,Shinya Takamaeda-Yamazaki","DeltaNet: Differential Binary Neural Networ","IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2019)",,,,,,2019,July
"大羽 由華,村上 大輔,中江 達哉,安藤 洸太,浅井 哲也,本村 真人,高前田 伸也","二値化ニューラルネットワークのハードウェア指向精度向上手法の検討","電子情報通信学会研究会報告CPSY2019-8",,,,,,2019,June
"池田 泰我,植吉 晃大,安藤 洸太,廣瀬 一俊,浅井 哲也,本村 真人,高前田 伸也","効率的なDNN計算のための無効ニューロン予測手法の評価","情報処理学会システム・アーキテクチャ研究会",,,,,,2019,June
"植吉 晃大,池田 泰我,安藤 洸太,廣瀬 一俊,浅井 哲也,高前田 伸也,本村 真人","無効ニューロン予測によるDNN計算効率化手法","電子情報通信学会研究会報告RECONF2019-18",,,,,,2019,May
"7.	安藤 洸太,植吉 晃大,大羽 由華,工藤 巧,池辺 将之,浅井 哲也,高前田 伸也,安藤 洸太,植吉 晃大,大羽 由華,廣瀬 一俊,工藤 巧,池辺 将之,浅井 哲也,高前田 伸也,本村 真人","Dither NN: 画像処理から着想を得た組込み向け量子化ニューラルネットワークの精度向上手法","電子情報通信学会研究会報告RECONF2019-14",,,,,,2019,May
"Ueyoshi K.,Ando K.,Hirose K,Takamaeda-Yamazaki S.,Hamada M.,Kurorda T.,Motomura M.","QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3D SRAM Using Inductive Coupling Technology in 40-nm CMOS",,"IEEE Journal of Solid-State Circuits",,"Vol. 54","No. 1",,2019,Jan.