"Miranda Enrique,Takamasa Kawanago,Kuniyuki KAKUSHIMA,J.Sune,HIROSHI IWAI","Modeling of the output characteristics of advanced n-MOSFETs after a severe gate-to-channel dielectric breakdown",,"[Microelectronic Engineering",,"Vol. 109",,"pp. 322-325",2013,Sept.
"Miranda Enrique,Takamasa Kawanago,Kuniyuki KAKUSHIMA,J. Sune,HIROSHI IWAI","Analysis and Simulation of the Postbreakdown I-V Characteristics of n-MOS Transistors in the Linear Response Regime",,"IEEE ELECTRON DEVICE LETTERS",,"Vol. 34","No. 6","pp. 798-800",2013,June
"Takamasa Kawanago,Kuniyuki KAKUSHIMA,ƒp�[ƒ‹ƒnƒbƒgƒAƒwƒ�ƒg,•Ð‰ª�D‘¥,Akira Nishiyama,Nobuyuki Sugii,KAZUO TSUTSUI,takeo hattori,Kenji Natori,HIROSHI IWAI","Comparative study of electrical characteristics in(100) and (110)surface-oriented nMOSFETs with direct contact La-silicate/Si interface structure",,"Solid-State Electronics",,"Vol. 84",,"pp. 53-57",2013,June
"T. Seki,T. Kawanago,K. Kakushima,P. Ahmet,Y. Kataoka,A. Nishiyama,N. Sugii,K. Tsutsui,K. Natori,T. Hattori,H. Iwai","Electrical and Infrared Absorption Studies on La-silicate/Si Interface","IEEE 2nd Int. Symp. on Next Generation Electronics (ISNE 2013)",,,,,,2013,Feb.
"Takamasa Kawanago,Kuniyuki KAKUSHIMA,ƒp�[ƒ‹ƒnƒbƒgƒAƒwƒ�ƒg,•Ð‰ª�D‘¥,�¼ŽR�²,Nobuyuki Sugii,KAZUO TSUTSUI,Kenji Natori,takeo hattori,HIROSHI IWAI","Interface properties of La-silicate gate dielectrics on Si(110)surface","Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology (WIMNACT 37)",,,,,,2013,
"�ì“ߎq�‚’¨,Šp“ˆ–M”V,Šâˆä—m","�‚‘¬�E’ᑹŽ¸‚Ì“dŽqƒfƒoƒCƒX�^ƒpƒ��[ƒfƒoƒCƒX‚Ì�擱Œ¤‹†","STARCƒ��[ƒNƒVƒ‡ƒbƒv2013",,,,,,2013,
"Takamasa Kawanago,Kuniyuki KAKUSHIMA,•Ð‰ª�D‘¥,Akira Nishiyama,Nobuyuki Sugii,Hitoshi Wakabayashi,KAZUO TSUTSUI,Kenji Natori,HIROSHI IWAI","Advantage of TiN Schottky Gate over Conventional Ni for Improved Electrical Characteristics in AlGaN/GaN HEMT","ESSDERC 2013",,,,,,2013,
"�@�´�C,�ì“ߎq�‚’¨,Šp“ˆ–M”V,•Ð‰ª�D‘¥,�¼ŽR�²,�™ˆä�M”V,Žá—Ñ�®,“›ˆäˆê�¶,–¼ŽæŒ¤“ñ,Šâˆä—m","ƒVƒ‡ƒbƒgƒL�[ƒQ�[ƒg�Þ—¿‚É‚æ‚éAlGaN/GaN‚Ì—e—Ê“dˆ³“Á�«‚ւ̉e‹¿","‘æ74‰ñ‰ž—p•¨—�Šw‰ï�H‹GŠw�p�u‰‰‰ï",,,,,,2013,
"Miranda Enrique,Takamasa Kawanago,Kuniyuki KAKUSHIMA,J. Sune,HIROSHI IWAI","Modeling of the Output Characteristics of Advanced N-MOSFETs After a Severe Gate-to-Channel Dielectric Breakdown","Insulating Films on Semiconductors(INFOS 2013)",,,,,,2013,
"ŠÖ‘ñ–ç,Takamasa Kawanago,Kuniyuki KAKUSHIMA,ƒp�[ƒ‹ƒnƒbƒgƒAƒwƒ�ƒg,•Ð‰ª�D‘¥,Akira Nishiyama,Nobuyuki Sugii,KAZUO TSUTSUI,Kenji Natori,takeo hattori,HIROSHI IWAI","International Symposium on Next-Generation Electronics(ISNE 2013)","International Symposium on Next-Generation Electronics(ISNE 2013)",,,,,,2013,
"ŠÖ‘ñ–ç,Takamasa Kawanago,Kuniyuki KAKUSHIMA,ƒp�[ƒ‹ƒnƒbƒgƒAƒwƒ�ƒg,•Ð‰ª�D‘¥,Akira Nishiyama,Nobuyuki Sugii,KAZUO TSUTSUI,Kenji Natori,takeo hattori,HIROSHI IWAI","Infrared absorption study of La-silicate gate dielectrics","Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology (WIMNACT 37)",,,,,,2013,
"Takamasa Kawanago,Kuniyuki KAKUSHIMA,ƒp�[ƒ‹ƒnƒbƒgƒAƒwƒ�ƒg,•Ð‰ª�D‘¥,Akira Nishiyama,Nobuyuki Sugii,KAZUO TSUTSUI,Kenji Natori,takeo hattori,HIROSHI IWAI","Interface properties of La-silicate gate dielectrics on Si(110)surface","Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology (WIMNACT 37)",,,,,,2013,
"Takamasa Kawanago,Yeonghun Lee,Kuniyuki KAKUSHIMA,ƒp�[ƒ‹ƒnƒbƒgƒAƒwƒ�ƒg,KAZUO TSUTSUI,�¼ŽR�²,Nobuyuki Sugii,Kenji Natori,takeo hattori,HIROSHI IWAI","Characterization of Effective Electron Mobility in n/MOSFETs with Direct Contact La-silicate/Si Structure","15th International Conference on Thin Films",,,,,,2013,
"Takamasa Kawanago,Kuniyuki KAKUSHIMA,ƒp�[ƒ‹ƒnƒbƒgƒAƒwƒ�ƒg,�¼ŽR�²,Nobuyuki Sugii,KAZUO TSUTSUI,KENJI NATORI,takeo hattori,HIROSHI IWAI","Nitrogen incorporated La-silicate gate dielectric with high scalability","[G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World�fs Leading Scientists",,,,,,2013,
"Takamasa Kawanago,Yeonghun Lee,Kuniyuki KAKUSHIMA,Ahmet Parhat,KAZUO TSUTSUI,�¼ŽR�²,Nobuyuki Sugii,Kenji Natori,takeo hattori,HIROSHI IWAI","Metal Inserted Poly-Si wirh High Temperature Annealing for Achieving EOT of 0.62nm in La-silicate MOSFET","41st European Solid-State Device Research Conference",,,,,,2013,