"�´–ì–«�m,ˆ«Žµ‘׎÷,�›Œ´‘�","CoFe/HfŒnŽ_‰»•¨/SiƒXƒsƒ“’�“üŒ¹‚Ì�ì�»‚Æ•]‰¿","‘æ21‰ñƒXƒsƒ“�HŠw‚ÌŠî‘b‚Ɖž—p (PASPS-21)",,,"  P-12",,,2016,Dec.
"–kŒ`‘åŽ÷,ˆ«Žµ‘׎÷,�›Œ´‘�","“dŠEƒAƒVƒXƒg4’[Žq”ñ‹Ç�ŠMOSƒfƒoƒCƒX‚̉ð�Í‚Æ�ÝŒv","‘æ21‰ñƒXƒsƒ“�HŠw‚ÌŠî‘b‚Ɖž—p (PASPS-21)",,,"  E-3",,,2016,Dec.
"Yota Takamura,Yusuke Shuto,Shu'uichiro Yamamoto,Hiroshi Funakubo,Minoru Kurosawa,Shigeki Nakagawa,Satoshi Sugahara","nverse-Magnetostriction-Induced Switching Current Reduction Technique for Spin-Transfer Torque MTJs and Its Low-Power MRAM Applications","2016 MRS Fall Meeting & Exhibit",,,,,,2016,Nov.
"Y. Takamura,Y. Shuto,S. Yamamoto,H. Funakubo,M. Kurosawa,S. Nakagawa,S. Sugahara","Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM",,"Solid-State Electron.",,"vol. 128","no. Supplement C","pp. 194-199",2016,Oct.
"Y. Shuto,S. Yamamoto,S. Sugahara","Energy Performance of Nonvolatile Power-Gating SRAM Using SOTB Technology","46th European Solid-State Device Conference",,,,,,2016,Sept.
"‹ß“¡�„,�ç˜e“ß�Ø,�›Œ´‘�","�‚–§“x�W�ω»”––Œƒgƒ‰ƒ“ƒXƒo�[ƒXŒ^ƒ}ƒCƒNƒ�”M“d”­“dƒ‚ƒWƒ…�[ƒ‹‚Ì�ÝŒv","‘æ13‰ñ“ú–{”M“dŠw‰ïŠw�p�u‰‰‰ï",,,"  S2B-6",,,2016,Sept.
"Y. Shuto,S. Yamamoto,S. Sugahara","Design and Implementation of Nonvolatile Power-Gating SRAM Using SOTB Technology","International Symposium on Low Power Electronics and Design, San Francisco",,,,,,2016,Aug.
"T. Akushichi,D. Kitagata,Y. Takamura,Y. Shuto,S. Sugahara","Spin Accumulation in a Si Channel using High-Quality CoFe/MgO/Si Spin Injectors","2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016)",,,"  P1-27",,,2016,June
"D. Kitagata,T. Akushichi,Y. Takamura,Y. Shuto,S. Sugahara","Robust Design of Electric-field-assisted Nonlocal Si-MOS Spin-devices","2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016)",,,"  P2-23",,,2016,June
"Y. Shuto,S. Yamamoto,S. Sugahara","Nonvolatile Power-gating Architecture for SRAM using SOTB Technology","016 IEEE Silicon Nanoelectronics Workshop (SNW 2016)",,,,,,2016,June
"Y. Shuto,S. Yamamoto,S. Sugahara","New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM","29th IEEE International Conference on Microelectronic Test Structures (ICMTS)",,,"  8-1",,,2016,Mar.
"Y. Takamura,Y. Shuto,S. Yamamoto,H. Funakubo,M.K. Kurosawa,S. Nakagawa,S. Sugahara","Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAMs","2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)",,,,"pp. 72-75",2016,Jan.